📄 stm32f10x_fsmc.lst
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327 /* Check the parameters */
328 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
329 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
330 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
331
332 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
333 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
334 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
335 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
336
337 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
338 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
339 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
340 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
341 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
342 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
343 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
344 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
345
346 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
347 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
348 FSMC_MemoryDataWidth_16b |
349 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
350 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
\ FSMC_PCCARDInit:
\ 00000000 0168 LDR R1,[R0, #+0]
\ 00000002 4268 LDR R2,[R0, #+4]
\ 00000004 51EA4221 ORRS R1,R1,R2, LSL #+9
\ 00000008 8268 LDR R2,[R0, #+8]
\ 0000000A 51EA4231 ORRS R1,R1,R2, LSL #+13
\ 0000000E 51F01001 ORRS R1,R1,#0x10
\ 00000012 ........ LDR.W R2,??DataTable15_9 ;; 0xa00000a0
\ 00000016 1160 STR R1,[R2, #+0]
351
352 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
353 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
354 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
355 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
356 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000018 C168 LDR R1,[R0, #+12]
\ 0000001A 0968 LDR R1,[R1, #+0]
\ 0000001C C268 LDR R2,[R0, #+12]
\ 0000001E 5268 LDR R2,[R2, #+4]
\ 00000020 51EA0221 ORRS R1,R1,R2, LSL #+8
\ 00000024 C268 LDR R2,[R0, #+12]
\ 00000026 9268 LDR R2,[R2, #+8]
\ 00000028 51EA0241 ORRS R1,R1,R2, LSL #+16
\ 0000002C C268 LDR R2,[R0, #+12]
\ 0000002E D268 LDR R2,[R2, #+12]
\ 00000030 51EA0261 ORRS R1,R1,R2, LSL #+24
\ 00000034 ........ LDR.W R2,??DataTable15_11 ;; 0xa00000a8
\ 00000038 1160 STR R1,[R2, #+0]
357
358 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
359 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
360 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
361 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
362 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 0000003A 0169 LDR R1,[R0, #+16]
\ 0000003C 0968 LDR R1,[R1, #+0]
\ 0000003E 0269 LDR R2,[R0, #+16]
\ 00000040 5268 LDR R2,[R2, #+4]
\ 00000042 51EA0221 ORRS R1,R1,R2, LSL #+8
\ 00000046 0269 LDR R2,[R0, #+16]
\ 00000048 9268 LDR R2,[R2, #+8]
\ 0000004A 51EA0241 ORRS R1,R1,R2, LSL #+16
\ 0000004E 0269 LDR R2,[R0, #+16]
\ 00000050 D268 LDR R2,[R2, #+12]
\ 00000052 51EA0261 ORRS R1,R1,R2, LSL #+24
\ 00000056 ........ LDR.W R2,??DataTable15_12 ;; 0xa00000ac
\ 0000005A 1160 STR R1,[R2, #+0]
363
364 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
365 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
366 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
367 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
368 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 0000005C 4169 LDR R1,[R0, #+20]
\ 0000005E 0968 LDR R1,[R1, #+0]
\ 00000060 4269 LDR R2,[R0, #+20]
\ 00000062 5268 LDR R2,[R2, #+4]
\ 00000064 51EA0221 ORRS R1,R1,R2, LSL #+8
\ 00000068 4269 LDR R2,[R0, #+20]
\ 0000006A 9268 LDR R2,[R2, #+8]
\ 0000006C 51EA0241 ORRS R1,R1,R2, LSL #+16
\ 00000070 4269 LDR R2,[R0, #+20]
\ 00000072 D268 LDR R2,[R2, #+12]
\ 00000074 51EA0261 ORRS R1,R1,R2, LSL #+24
\ 00000078 ........ LDR.W R2,??DataTable15_13 ;; 0xa00000b0
\ 0000007C 1160 STR R1,[R2, #+0]
369 }
\ 0000007E 7047 BX LR ;; return
370
371 /**
372 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
373 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
374 * structure which will be initialized.
375 * @retval None
376 */
\ In section .text, align 2, keep-with-next
377 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
378 {
379 /* Reset NOR/SRAM Init structure parameters values */
380 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
\ FSMC_NORSRAMStructInit:
\ 00000000 0021 MOVS R1,#+0
\ 00000002 0160 STR R1,[R0, #+0]
381 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
\ 00000004 0221 MOVS R1,#+2
\ 00000006 4160 STR R1,[R0, #+4]
382 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
\ 00000008 0021 MOVS R1,#+0
\ 0000000A 8160 STR R1,[R0, #+8]
383 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
\ 0000000C 0021 MOVS R1,#+0
\ 0000000E C160 STR R1,[R0, #+12]
384 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
\ 00000010 0021 MOVS R1,#+0
\ 00000012 0161 STR R1,[R0, #+16]
385 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
\ 00000014 0021 MOVS R1,#+0
\ 00000016 4161 STR R1,[R0, #+20]
386 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
\ 00000018 0021 MOVS R1,#+0
\ 0000001A 8161 STR R1,[R0, #+24]
387 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
\ 0000001C 0021 MOVS R1,#+0
\ 0000001E C161 STR R1,[R0, #+28]
388 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
\ 00000020 0021 MOVS R1,#+0
\ 00000022 0162 STR R1,[R0, #+32]
389 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
\ 00000024 4FF48051 MOV R1,#+4096
\ 00000028 4162 STR R1,[R0, #+36]
390 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
\ 0000002A 4FF40051 MOV R1,#+8192
\ 0000002E 8162 STR R1,[R0, #+40]
391 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
\ 00000030 0021 MOVS R1,#+0
\ 00000032 C162 STR R1,[R0, #+44]
392 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
\ 00000034 0021 MOVS R1,#+0
\ 00000036 0163 STR R1,[R0, #+48]
393 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
\ 00000038 416B LDR R1,[R0, #+52]
\ 0000003A 0F22 MOVS R2,#+15
\ 0000003C 0A60 STR R2,[R1, #+0]
394 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
\ 0000003E 416B LDR R1,[R0, #+52]
\ 00000040 0F22 MOVS R2,#+15
\ 00000042 4A60 STR R2,[R1, #+4]
395 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
\ 00000044 416B LDR R1,[R0, #+52]
\ 00000046 FF22 MOVS R2,#+255
\ 00000048 8A60 STR R2,[R1, #+8]
396 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
\ 0000004A 416B LDR R1,[R0, #+52]
\ 0000004C 0F22 MOVS R2,#+15
\ 0000004E CA60 STR R2,[R1, #+12]
397 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
\ 00000050 416B LDR R1,[R0, #+52]
\ 00000052 0F22 MOVS R2,#+15
\ 00000054 0A61 STR R2,[R1, #+16]
398 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
\ 00000056 416B LDR R1,[R0, #+52]
\ 00000058 0F22 MOVS R2,#+15
\ 0000005A 4A61 STR R2,[R1, #+20]
399 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
\ 0000005C 416B LDR R1,[R0, #+52]
\ 0000005E 0022 MOVS R2,#+0
\ 00000060 8A61 STR R2,[R1, #+24]
400 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
\ 00000062 816B LDR R1,[R0, #+56]
\ 00000064 0F22 MOVS R2,#+15
\ 00000066 0A60 STR R2,[R1, #+0]
401 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
\ 00000068 816B LDR R1,[R0, #+56]
\ 0000006A 0F22 MOVS R2,#+15
\ 0000006C 4A60 STR R2,[R1, #+4]
402 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
\ 0000006E 816B LDR R1,[R0, #+56]
\ 00000070 FF22 MOVS R2,#+255
\ 00000072 8A60 STR R2,[R1, #+8]
403 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
\ 00000074 816B LDR R1,[R0, #+56]
\ 00000076 0F22 MOVS R2,#+15
\ 00000078 CA60 STR R2,[R1, #+12]
404 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
\ 0000007A 816B LDR R1,[R0, #+56]
\ 0000007C 0F22 MOVS R2,#+15
\ 0000007E 0A61 STR R2,[R1, #+16]
405 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
\ 00000080 816B LDR R1,[R0, #+56]
\ 00000082 0F22 MOVS R2,#+15
\ 00000084 4A61 STR R2,[R1, #+20]
406 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
\ 00000086 816B LDR R1,[R0, #+56]
\ 00000088 0022 MOVS R2,#+0
\ 0000008A 8A61 STR R2,[R1, #+24]
407 }
\ 0000008C 7047 BX LR ;; return
408
409 /**
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