📄 stm32f10x_fsmc.lst
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\ 0000007E 51EA0261 ORRS R1,R1,R2, LSL #+24
\ 00000082 426B LDR R2,[R0, #+52]
\ 00000084 9269 LDR R2,[R2, #+24]
\ 00000086 1143 ORRS R1,R2,R1
\ 00000088 0268 LDR R2,[R0, #+0]
\ 0000008A 9200 LSLS R2,R2,#+2
\ 0000008C B2F1C042 SUBS R2,R2,#+1610612736
\ 00000090 5160 STR R1,[R2, #+4]
228
229
230 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
231 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
\ 00000092 C16A LDR R1,[R0, #+44]
\ 00000094 B1F5804F CMP R1,#+16384
\ 00000098 1AD1 BNE.N ??FSMC_NORSRAMInit_1
232 {
233 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
234 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
235 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
236 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
237 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
238 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
239 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
240 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
241 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
242 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
243 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
244 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
245 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
\ 0000009A 816B LDR R1,[R0, #+56]
\ 0000009C 0968 LDR R1,[R1, #+0]
\ 0000009E 826B LDR R2,[R0, #+56]
\ 000000A0 5268 LDR R2,[R2, #+4]
\ 000000A2 51EA0211 ORRS R1,R1,R2, LSL #+4
\ 000000A6 826B LDR R2,[R0, #+56]
\ 000000A8 9268 LDR R2,[R2, #+8]
\ 000000AA 51EA0221 ORRS R1,R1,R2, LSL #+8
\ 000000AE 826B LDR R2,[R0, #+56]
\ 000000B0 1269 LDR R2,[R2, #+16]
\ 000000B2 51EA0251 ORRS R1,R1,R2, LSL #+20
\ 000000B6 826B LDR R2,[R0, #+56]
\ 000000B8 5269 LDR R2,[R2, #+20]
\ 000000BA 51EA0261 ORRS R1,R1,R2, LSL #+24
\ 000000BE 826B LDR R2,[R0, #+56]
\ 000000C0 9269 LDR R2,[R2, #+24]
\ 000000C2 1143 ORRS R1,R2,R1
\ 000000C4 0268 LDR R2,[R0, #+0]
\ 000000C6 ........ LDR.W R3,??DataTable15 ;; 0xa0000104
\ 000000CA 43F82210 STR R1,[R3, R2, LSL #+2]
\ 000000CE 06E0 B.N ??FSMC_NORSRAMInit_2
246 }
247 else
248 {
249 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
\ ??FSMC_NORSRAMInit_1:
\ 000000D0 0168 LDR R1,[R0, #+0]
\ 000000D2 ........ LDR.W R2,??DataTable15 ;; 0xa0000104
\ 000000D6 7FF07043 MVNS R3,#-268435456
\ 000000DA 42F82130 STR R3,[R2, R1, LSL #+2]
250 }
251 }
\ ??FSMC_NORSRAMInit_2:
\ 000000DE 7047 BX LR ;; return
252
253 /**
254 * @brief Initializes the FSMC NAND Banks according to the specified
255 * parameters in the FSMC_NANDInitStruct.
256 * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
257 * structure that contains the configuration information for the FSMC NAND specified Banks.
258 * @retval None
259 */
\ In section .text, align 2, keep-with-next
260 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
261 {
\ FSMC_NANDInit:
\ 00000000 30B4 PUSH {R4,R5}
262 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
\ 00000002 0021 MOVS R1,#+0
\ 00000004 0022 MOVS R2,#+0
\ 00000006 0023 MOVS R3,#+0
263
264 /* Check the parameters */
265 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
266 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
267 assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
268 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
269 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
270 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
271 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
272 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
273 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
274 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
275 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
276 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
277 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
278 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
279 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
280
281 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
282 tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
283 PCR_MemoryType_NAND |
284 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
285 FSMC_NANDInitStruct->FSMC_ECC |
286 FSMC_NANDInitStruct->FSMC_ECCPageSize |
287 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
288 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
\ 00000008 4468 LDR R4,[R0, #+4]
\ 0000000A 8568 LDR R5,[R0, #+8]
\ 0000000C 2C43 ORRS R4,R5,R4
\ 0000000E C568 LDR R5,[R0, #+12]
\ 00000010 2C43 ORRS R4,R5,R4
\ 00000012 0569 LDR R5,[R0, #+16]
\ 00000014 2C43 ORRS R4,R5,R4
\ 00000016 4569 LDR R5,[R0, #+20]
\ 00000018 54EA4524 ORRS R4,R4,R5, LSL #+9
\ 0000001C 8569 LDR R5,[R0, #+24]
\ 0000001E 54EA4534 ORRS R4,R4,R5, LSL #+13
\ 00000022 54F00804 ORRS R4,R4,#0x8
\ 00000026 2100 MOVS R1,R4
289
290 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
291 tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
292 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
293 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
294 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000028 C469 LDR R4,[R0, #+28]
\ 0000002A 2468 LDR R4,[R4, #+0]
\ 0000002C C569 LDR R5,[R0, #+28]
\ 0000002E 6D68 LDR R5,[R5, #+4]
\ 00000030 54EA0524 ORRS R4,R4,R5, LSL #+8
\ 00000034 C569 LDR R5,[R0, #+28]
\ 00000036 AD68 LDR R5,[R5, #+8]
\ 00000038 54EA0544 ORRS R4,R4,R5, LSL #+16
\ 0000003C C569 LDR R5,[R0, #+28]
\ 0000003E ED68 LDR R5,[R5, #+12]
\ 00000040 54EA0564 ORRS R4,R4,R5, LSL #+24
\ 00000044 2200 MOVS R2,R4
295
296 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
297 tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
298 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
299 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
300 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000046 046A LDR R4,[R0, #+32]
\ 00000048 2468 LDR R4,[R4, #+0]
\ 0000004A 056A LDR R5,[R0, #+32]
\ 0000004C 6D68 LDR R5,[R5, #+4]
\ 0000004E 54EA0524 ORRS R4,R4,R5, LSL #+8
\ 00000052 056A LDR R5,[R0, #+32]
\ 00000054 AD68 LDR R5,[R5, #+8]
\ 00000056 54EA0544 ORRS R4,R4,R5, LSL #+16
\ 0000005A 056A LDR R5,[R0, #+32]
\ 0000005C ED68 LDR R5,[R5, #+12]
\ 0000005E 54EA0564 ORRS R4,R4,R5, LSL #+24
\ 00000062 2300 MOVS R3,R4
301
302 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
\ 00000064 0468 LDR R4,[R0, #+0]
\ 00000066 102C CMP R4,#+16
\ 00000068 09D1 BNE.N ??FSMC_NANDInit_0
303 {
304 /* FSMC_Bank2_NAND registers configuration */
305 FSMC_Bank2->PCR2 = tmppcr;
\ 0000006A ........ LDR.W R4,??DataTable15_1 ;; 0xa0000060
\ 0000006E 2160 STR R1,[R4, #+0]
306 FSMC_Bank2->PMEM2 = tmppmem;
\ 00000070 ........ LDR.W R4,??DataTable15_3 ;; 0xa0000068
\ 00000074 2260 STR R2,[R4, #+0]
307 FSMC_Bank2->PATT2 = tmppatt;
\ 00000076 ........ LDR.W R4,??DataTable15_4 ;; 0xa000006c
\ 0000007A 2360 STR R3,[R4, #+0]
\ 0000007C 08E0 B.N ??FSMC_NANDInit_1
308 }
309 else
310 {
311 /* FSMC_Bank3_NAND registers configuration */
312 FSMC_Bank3->PCR3 = tmppcr;
\ ??FSMC_NANDInit_0:
\ 0000007E ........ LDR.W R4,??DataTable15_5 ;; 0xa0000080
\ 00000082 2160 STR R1,[R4, #+0]
313 FSMC_Bank3->PMEM3 = tmppmem;
\ 00000084 ........ LDR.W R4,??DataTable15_7 ;; 0xa0000088
\ 00000088 2260 STR R2,[R4, #+0]
314 FSMC_Bank3->PATT3 = tmppatt;
\ 0000008A ........ LDR.W R4,??DataTable15_8 ;; 0xa000008c
\ 0000008E 2360 STR R3,[R4, #+0]
315 }
316 }
\ ??FSMC_NANDInit_1:
\ 00000090 30BC POP {R4,R5}
\ 00000092 7047 BX LR ;; return
317
318 /**
319 * @brief Initializes the FSMC PCCARD Bank according to the specified
320 * parameters in the FSMC_PCCARDInitStruct.
321 * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
322 * structure that contains the configuration information for the FSMC PCCARD Bank.
323 * @retval None
324 */
\ In section .text, align 2, keep-with-next
325 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
326 {
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