stm32f10x_fsmc.lst
来自「stm32+ucos-ii」· LST 代码 · 共 1,020 行 · 第 1/5 页
LST
1,020 行
133 if(FSMC_Bank == FSMC_Bank2_NAND)
\ FSMC_NANDDeInit:
\ 00000000 1028 CMP R0,#+16
\ 00000002 12D1 BNE.N ??FSMC_NANDDeInit_0
134 {
135 /* Set the FSMC_Bank2 registers to their reset values */
136 FSMC_Bank2->PCR2 = 0x00000018;
\ 00000004 ........ LDR.W R1,??DataTable15_1 ;; 0xa0000060
\ 00000008 1822 MOVS R2,#+24
\ 0000000A 0A60 STR R2,[R1, #+0]
137 FSMC_Bank2->SR2 = 0x00000040;
\ 0000000C ........ LDR.W R1,??DataTable15_2 ;; 0xa0000064
\ 00000010 4022 MOVS R2,#+64
\ 00000012 0A60 STR R2,[R1, #+0]
138 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
\ 00000014 ........ LDR.W R1,??DataTable15_3 ;; 0xa0000068
\ 00000018 5FF0FC32 MOVS R2,#-50529028
\ 0000001C 0A60 STR R2,[R1, #+0]
139 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
\ 0000001E ........ LDR.W R1,??DataTable15_4 ;; 0xa000006c
\ 00000022 5FF0FC32 MOVS R2,#-50529028
\ 00000026 0A60 STR R2,[R1, #+0]
\ 00000028 11E0 B.N ??FSMC_NANDDeInit_1
140 }
141 /* FSMC_Bank3_NAND */
142 else
143 {
144 /* Set the FSMC_Bank3 registers to their reset values */
145 FSMC_Bank3->PCR3 = 0x00000018;
\ ??FSMC_NANDDeInit_0:
\ 0000002A ........ LDR.W R1,??DataTable15_5 ;; 0xa0000080
\ 0000002E 1822 MOVS R2,#+24
\ 00000030 0A60 STR R2,[R1, #+0]
146 FSMC_Bank3->SR3 = 0x00000040;
\ 00000032 ........ LDR.W R1,??DataTable15_6 ;; 0xa0000084
\ 00000036 4022 MOVS R2,#+64
\ 00000038 0A60 STR R2,[R1, #+0]
147 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
\ 0000003A ........ LDR.W R1,??DataTable15_7 ;; 0xa0000088
\ 0000003E 5FF0FC32 MOVS R2,#-50529028
\ 00000042 0A60 STR R2,[R1, #+0]
148 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
\ 00000044 ........ LDR.W R1,??DataTable15_8 ;; 0xa000008c
\ 00000048 5FF0FC32 MOVS R2,#-50529028
\ 0000004C 0A60 STR R2,[R1, #+0]
149 }
150 }
\ ??FSMC_NANDDeInit_1:
\ 0000004E 7047 BX LR ;; return
151
152 /**
153 * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
154 * @param None
155 * @retval None
156 */
\ In section .text, align 2, keep-with-next
157 void FSMC_PCCARDDeInit(void)
158 {
159 /* Set the FSMC_Bank4 registers to their reset values */
160 FSMC_Bank4->PCR4 = 0x00000018;
\ FSMC_PCCARDDeInit:
\ 00000000 ........ LDR.W R0,??DataTable15_9 ;; 0xa00000a0
\ 00000004 1821 MOVS R1,#+24
\ 00000006 0160 STR R1,[R0, #+0]
161 FSMC_Bank4->SR4 = 0x00000000;
\ 00000008 ........ LDR.W R0,??DataTable15_10 ;; 0xa00000a4
\ 0000000C 0021 MOVS R1,#+0
\ 0000000E 0160 STR R1,[R0, #+0]
162 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
\ 00000010 ........ LDR.W R0,??DataTable15_11 ;; 0xa00000a8
\ 00000014 5FF0FC31 MOVS R1,#-50529028
\ 00000018 0160 STR R1,[R0, #+0]
163 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
\ 0000001A ........ LDR.W R0,??DataTable15_12 ;; 0xa00000ac
\ 0000001E 5FF0FC31 MOVS R1,#-50529028
\ 00000022 0160 STR R1,[R0, #+0]
164 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
\ 00000024 ........ LDR.W R0,??DataTable15_13 ;; 0xa00000b0
\ 00000028 5FF0FC31 MOVS R1,#-50529028
\ 0000002C 0160 STR R1,[R0, #+0]
165 }
\ 0000002E 7047 BX LR ;; return
166
167 /**
168 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
169 * parameters in the FSMC_NORSRAMInitStruct.
170 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
171 * structure that contains the configuration information for
172 * the FSMC NOR/SRAM specified Banks.
173 * @retval None
174 */
\ In section .text, align 2, keep-with-next
175 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
176 {
177 /* Check the parameters */
178 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
179 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
180 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
181 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
182 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
183 assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
184 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
185 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
186 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
187 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
188 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
189 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
190 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
191 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
192 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
193 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
194 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
195 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
196 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
197 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
198
199 /* Bank1 NOR/SRAM control register configuration */
200 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
201 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
202 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
203 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
204 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
205 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
206 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
207 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
208 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
209 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
210 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
211 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
212 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
\ FSMC_NORSRAMInit:
\ 00000000 4168 LDR R1,[R0, #+4]
\ 00000002 8268 LDR R2,[R0, #+8]
\ 00000004 1143 ORRS R1,R2,R1
\ 00000006 C268 LDR R2,[R0, #+12]
\ 00000008 1143 ORRS R1,R2,R1
\ 0000000A 0269 LDR R2,[R0, #+16]
\ 0000000C 1143 ORRS R1,R2,R1
\ 0000000E 4269 LDR R2,[R0, #+20]
\ 00000010 1143 ORRS R1,R2,R1
\ 00000012 8269 LDR R2,[R0, #+24]
\ 00000014 1143 ORRS R1,R2,R1
\ 00000016 C269 LDR R2,[R0, #+28]
\ 00000018 1143 ORRS R1,R2,R1
\ 0000001A 026A LDR R2,[R0, #+32]
\ 0000001C 1143 ORRS R1,R2,R1
\ 0000001E 426A LDR R2,[R0, #+36]
\ 00000020 1143 ORRS R1,R2,R1
\ 00000022 826A LDR R2,[R0, #+40]
\ 00000024 1143 ORRS R1,R2,R1
\ 00000026 C26A LDR R2,[R0, #+44]
\ 00000028 1143 ORRS R1,R2,R1
\ 0000002A 026B LDR R2,[R0, #+48]
\ 0000002C 1143 ORRS R1,R2,R1
\ 0000002E 0268 LDR R2,[R0, #+0]
\ 00000030 9200 LSLS R2,R2,#+2
\ 00000032 B2F1C042 SUBS R2,R2,#+1610612736
\ 00000036 1160 STR R1,[R2, #+0]
213
214 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
\ 00000038 8168 LDR R1,[R0, #+8]
\ 0000003A 0829 CMP R1,#+8
\ 0000003C 0BD1 BNE.N ??FSMC_NORSRAMInit_0
215 {
216 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
\ 0000003E 0168 LDR R1,[R0, #+0]
\ 00000040 8900 LSLS R1,R1,#+2
\ 00000042 B1F1C041 SUBS R1,R1,#+1610612736
\ 00000046 0968 LDR R1,[R1, #+0]
\ 00000048 51F04001 ORRS R1,R1,#0x40
\ 0000004C 0268 LDR R2,[R0, #+0]
\ 0000004E 9200 LSLS R2,R2,#+2
\ 00000050 B2F1C042 SUBS R2,R2,#+1610612736
\ 00000054 1160 STR R1,[R2, #+0]
217 }
218
219 /* Bank1 NOR/SRAM timing register configuration */
220 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
221 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
222 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
223 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
224 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
225 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
226 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
227 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
\ ??FSMC_NORSRAMInit_0:
\ 00000056 416B LDR R1,[R0, #+52]
\ 00000058 0968 LDR R1,[R1, #+0]
\ 0000005A 426B LDR R2,[R0, #+52]
\ 0000005C 5268 LDR R2,[R2, #+4]
\ 0000005E 51EA0211 ORRS R1,R1,R2, LSL #+4
\ 00000062 426B LDR R2,[R0, #+52]
\ 00000064 9268 LDR R2,[R2, #+8]
\ 00000066 51EA0221 ORRS R1,R1,R2, LSL #+8
\ 0000006A 426B LDR R2,[R0, #+52]
\ 0000006C D268 LDR R2,[R2, #+12]
\ 0000006E 51EA0241 ORRS R1,R1,R2, LSL #+16
\ 00000072 426B LDR R2,[R0, #+52]
\ 00000074 1269 LDR R2,[R2, #+16]
\ 00000076 51EA0251 ORRS R1,R1,R2, LSL #+20
\ 0000007A 426B LDR R2,[R0, #+52]
\ 0000007C 5269 LDR R2,[R2, #+20]
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