📄 cpu_c.lst
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\ 00000056 90FBF1F0 SDIV R0,R0,R1
\ 0000005A 0500 MOVS R5,R0
469 nbr = (pos - 16) % 32;
\ 0000005C E4B2 UXTB R4,R4 ;; ZeroExt R4,R4,#+24,#+24
\ 0000005E B4F11000 SUBS R0,R4,#+16
\ 00000062 2021 MOVS R1,#+32
\ 00000064 90FBF1F2 SDIV R2,R0,R1
\ 00000068 02FB1102 MLS R2,R2,R1,R0
\ 0000006C 1600 MOVS R6,R2
470
471 CPU_CRITICAL_ENTER();
\ 0000006E ........ BL CPU_SR_Save
\ 00000072 8046 MOV R8,R0
472 CPU_REG_NVIC_CLRPEND(group) = DEF_BIT(nbr);
\ 00000074 EDB2 UXTB R5,R5 ;; ZeroExt R5,R5,#+24,#+24
\ 00000076 ........ LDR.W R0,??DataTable6_7 ;; 0xe000e280
\ 0000007A 0121 MOVS R1,#+1
\ 0000007C B140 LSLS R1,R1,R6
\ 0000007E 40F82510 STR R1,[R0, R5, LSL #+2]
473 CPU_CRITICAL_EXIT();
\ 00000082 4046 MOV R0,R8
\ 00000084 ........ BL CPU_SR_Restore
474 }
475 break;
476 }
477 }
\ ??CPU_IntSrcPendClr_4:
\ ??CPU_IntSrcPendClr_3:
\ 00000088 BDE8F081 POP {R4-R8,PC} ;; return
478
479
480 /*$PAGE*/
481 /*
482 *********************************************************************************************************
483 * CPU_IntSrcPrioSet()
484 *
485 * Description : Set priority of an interrupt source.
486 *
487 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
488 *
489 * prio Priority. Use a lower priority number for a higher priority.
490 *
491 * Return(s) : none.
492 *
493 * Caller(s) : Application.
494 *
495 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
496 *
497 * (2) Several interrupts priorities CANNOT be set :
498 *
499 * (a) Reset (always -3).
500 * (b) NMI (always -2).
501 * (c) Hard fault (always -1).
502 *
503 * (3) See 'CPU_IntSrcDis() Note #3'.
504 *********************************************************************************************************
505 */
506
\ In section .text, align 2, keep-with-next
507 void CPU_IntSrcPrioSet (CPU_INT08U pos,
508 CPU_INT08U prio)
509 {
\ CPU_IntSrcPrioSet:
\ 00000000 2DE9F84F PUSH {R3-R11,LR}
\ 00000004 0400 MOVS R4,R0
\ 00000006 0D00 MOVS R5,R1
510 CPU_INT08U group;
511 CPU_INT08U nbr;
512 CPU_INT08U pos_max;
513 CPU_INT32U prio_32;
514 CPU_INT32U temp;
515 CPU_SR_ALLOC();
\ 00000008 5FF0000B MOVS R11,#+0
516
517
518 prio_32 = CPU_RevBits((CPU_INT08U)prio);
\ 0000000C EDB2 UXTB R5,R5 ;; ZeroExt R5,R5,#+24,#+24
\ 0000000E 2800 MOVS R0,R5
\ 00000010 ........ BL CPU_RevBits
\ 00000014 8146 MOV R9,R0
519 prio = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
\ 00000016 5FEA1960 LSRS R0,R9,#+24
\ 0000001A 0500 MOVS R5,R0
520
521 switch (pos) {
\ 0000001C E4B2 UXTB R4,R4 ;; ZeroExt R4,R4,#+24,#+24
\ 0000001E 002C CMP R4,#+0
\ 00000020 17D0 BEQ.N ??CPU_IntSrcPrioSet_0
\ 00000022 022C CMP R4,#+2
\ 00000024 16D0 BEQ.N ??CPU_IntSrcPrioSet_1
\ 00000026 15D3 BCC.N ??CPU_IntSrcPrioSet_1
\ 00000028 042C CMP R4,#+4
\ 0000002A 14D0 BEQ.N ??CPU_IntSrcPrioSet_2
\ 0000002C 12D3 BCC.N ??CPU_IntSrcPrioSet_1
\ 0000002E 062C CMP R4,#+6
\ 00000030 37D0 BEQ.N ??CPU_IntSrcPrioSet_3
\ 00000032 24D3 BCC.N ??CPU_IntSrcPrioSet_4
\ 00000034 082C CMP R4,#+8
\ 00000036 0CD0 BEQ.N ??CPU_IntSrcPrioSet_0
\ 00000038 0BD3 BCC.N ??CPU_IntSrcPrioSet_0
\ 0000003A 0A2C CMP R4,#+10
\ 0000003C 09D0 BEQ.N ??CPU_IntSrcPrioSet_0
\ 0000003E 08D3 BCC.N ??CPU_IntSrcPrioSet_0
\ 00000040 0C2C CMP R4,#+12
\ 00000042 54D0 BEQ.N ??CPU_IntSrcPrioSet_5
\ 00000044 3FD3 BCC.N ??CPU_IntSrcPrioSet_6
\ 00000046 0E2C CMP R4,#+14
\ 00000048 65D0 BEQ.N ??CPU_IntSrcPrioSet_7
\ 0000004A 02D3 BCC.N ??CPU_IntSrcPrioSet_0
\ 0000004C 0F2C CMP R4,#+15
\ 0000004E 74D0 BEQ.N ??CPU_IntSrcPrioSet_8
\ 00000050 87E0 B.N ??CPU_IntSrcPrioSet_9
522 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
523 case CPU_INT_RSVD_07:
524 case CPU_INT_RSVD_08:
525 case CPU_INT_RSVD_09:
526 case CPU_INT_RSVD_10:
527 case CPU_INT_RSVD_13:
528 break;
\ ??CPU_IntSrcPrioSet_0:
\ 00000052 BFE0 B.N ??CPU_IntSrcPrioSet_10
529
530
531 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
532 case CPU_INT_RESET: /* Reset (see Note #2). */
533 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
534 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
535 break;
\ ??CPU_IntSrcPrioSet_1:
\ 00000054 BEE0 B.N ??CPU_IntSrcPrioSet_10
536
537 case CPU_INT_MEM: /* Memory management. */
538 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_2:
\ 00000056 ........ BL CPU_SR_Save
\ 0000005A 8346 MOV R11,R0
539 temp = CPU_REG_NVIC_SHPRI1;
\ 0000005C .... LDR.N R0,??DataTable6_8 ;; 0xe000ed18
\ 0000005E 0068 LDR R0,[R0, #+0]
\ 00000060 8246 MOV R10,R0
540 temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
\ 00000062 5FEA1A2A LSRS R10,R10,#+8
\ 00000066 5FEA0A2A LSLS R10,R10,#+8
541 temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
\ 0000006A EDB2 UXTB R5,R5 ;; ZeroExt R5,R5,#+24,#+24
\ 0000006C 55EA0A0A ORRS R10,R5,R10
542 CPU_REG_NVIC_SHPRI1 = temp;
\ 00000070 .... LDR.N R0,??DataTable6_8 ;; 0xe000ed18
\ 00000072 C0F800A0 STR R10,[R0, #+0]
543 CPU_CRITICAL_EXIT();
\ 00000076 5846 MOV R0,R11
\ 00000078 ........ BL CPU_SR_Restore
544 break;
\ 0000007C AAE0 B.N ??CPU_IntSrcPrioSet_10
545
546 case CPU_INT_BUSFAULT: /* Bus fault. */
547 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_4:
\ 0000007E ........ BL CPU_SR_Save
\ 00000082 8346 MOV R11,R0
548 temp = CPU_REG_NVIC_SHPRI1;
\ 00000084 .... LDR.N R0,??DataTable6_8 ;; 0xe000ed18
\ 00000086 0068 LDR R0,[R0, #+0]
\ 00000088 8246 MOV R10,R0
549 temp &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
\ 0000008A 3AF47F4A BICS R10,R10,#0xFF00
550 temp |= (prio << (1 * DEF_OCTET_NBR_BITS));
\ 0000008E EDB2 UXTB R5,R5 ;; ZeroExt R5,R5,#+24,#+24
\ 00000090 5AEA052A ORRS R10,R10,R5, LSL #+8
551 CPU_REG_NVIC_SHPRI1 = temp;
\ 00000094 .... LDR.N R0,??DataTable6_8 ;; 0xe000ed18
\ 00000096 C0F800A0 STR R10,[R0, #+0]
552 CPU_CRITICAL_EXIT();
\ 0000009A 5846 MOV R0,R11
\ 0000009C ........ BL CPU_SR_Restore
553 break;
\ 000000A0 98E0 B.N ??CPU_IntSrcPrioSet_10
554
555 case CPU_INT_USAGEFAULT: /* Usage fault. */
556 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_3:
\ 000000A2 ........ BL CPU_SR_Save
\ 000000A6 8346 MOV R11,R0
557 temp = CPU_REG_NVIC_SHPRI1;
\ 000000A8 .... LDR.N R0,??DataTable6_8 ;; 0xe000ed18
\ 000000AA 0068 LDR R0,[R0, #+0]
\ 000000AC 8246 MOV R10,R0
558 temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
\ 000000AE 3AF47F0A BICS R10,R10,#0xFF0000
559 temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
\ 000000B2 EDB2 UXTB R5,R5 ;; ZeroExt R5,R5,#+24,#+24
\ 000000B4 5AEA054A ORRS R10,R10,R5, LSL #+16
560 CPU_REG_NVIC_SHPRI1 = temp;
\ 000000B8 .... LDR.N R0,??DataTable6_8 ;; 0xe000ed18
\ 000000BA C0F800A0 STR R10,[R0, #+0]
561 CPU_CRITICAL_EXIT();
\ 000000BE 5846 MOV R0,R11
\ 000000C0 ........ BL CPU_SR_Restore
562 break;
\ 000000C4 86E0 B.N ??CPU_IntSrcPrioSet_10
563
564 case CPU_INT_SVCALL: /* SVCall. */
565 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_6:
\ 000000C6 ........ BL CPU_SR_Save
\ 000000CA 8346 MOV R11,R0
566 temp = CPU_REG_NVIC_SHPRI2;
\ 000000CC .... LDR.N R0,??DataTable6_9 ;; 0xe000ed1c
\ 000000CE 0068 LDR R0,[R0, #+0]
\ 000000D0 8246 MOV R10,R0
567 temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
\ 000000D2 5FEA0A2A LSLS R10,R10,#+8 ;; ZeroExtS R10,R10,#+8,#+8
\ 000000D6 5FEA1A2A LSRS R10,R10,#+8
568 temp |= (prio ⌨️ 快捷键说明
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