📄 cpu_c.lst
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\ 00000044 ........ BL CPU_SR_Save
\ 00000048 8046 MOV R8,R0
276 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
\ 0000004A ........ LDR.W R0,??DataTable6_2 ;; 0xe000ed24
\ 0000004E 0068 LDR R0,[R0, #+0]
\ 00000050 30F48030 BICS R0,R0,#0x10000
\ 00000054 ........ LDR.W R1,??DataTable6_2 ;; 0xe000ed24
\ 00000058 0860 STR R0,[R1, #+0]
277 CPU_CRITICAL_EXIT();
\ 0000005A 4046 MOV R0,R8
\ 0000005C ........ BL CPU_SR_Restore
278 break;
\ 00000060 56E0 B.N ??CPU_IntSrcDis_7
279
280 case CPU_INT_BUSFAULT: /* Bus fault. */
281 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_4:
\ 00000062 ........ BL CPU_SR_Save
\ 00000066 8046 MOV R8,R0
282 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
\ 00000068 ........ LDR.W R0,??DataTable6_2 ;; 0xe000ed24
\ 0000006C 0068 LDR R0,[R0, #+0]
\ 0000006E 30F40030 BICS R0,R0,#0x20000
\ 00000072 ........ LDR.W R1,??DataTable6_2 ;; 0xe000ed24
\ 00000076 0860 STR R0,[R1, #+0]
283 CPU_CRITICAL_EXIT();
\ 00000078 4046 MOV R0,R8
\ 0000007A ........ BL CPU_SR_Restore
284 break;
\ 0000007E 47E0 B.N ??CPU_IntSrcDis_7
285
286 case CPU_INT_USAGEFAULT: /* Usage fault. */
287 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_3:
\ 00000080 ........ BL CPU_SR_Save
\ 00000084 8046 MOV R8,R0
288 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
\ 00000086 ........ LDR.W R0,??DataTable6_2 ;; 0xe000ed24
\ 0000008A 0068 LDR R0,[R0, #+0]
\ 0000008C 30F48020 BICS R0,R0,#0x40000
\ 00000090 ........ LDR.W R1,??DataTable6_2 ;; 0xe000ed24
\ 00000094 0860 STR R0,[R1, #+0]
289 CPU_CRITICAL_EXIT();
\ 00000096 4046 MOV R0,R8
\ 00000098 ........ BL CPU_SR_Restore
290 break;
\ 0000009C 38E0 B.N ??CPU_IntSrcDis_7
291
292 case CPU_INT_SYSTICK: /* SysTick. */
293 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_5:
\ 0000009E ........ BL CPU_SR_Save
\ 000000A2 8046 MOV R8,R0
294 CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
\ 000000A4 ........ LDR.W R0,??DataTable6_3 ;; 0xe000e010
\ 000000A8 0068 LDR R0,[R0, #+0]
\ 000000AA 4008 LSRS R0,R0,#+1
\ 000000AC 4000 LSLS R0,R0,#+1
\ 000000AE ........ LDR.W R1,??DataTable6_3 ;; 0xe000e010
\ 000000B2 0860 STR R0,[R1, #+0]
295 CPU_CRITICAL_EXIT();
\ 000000B4 4046 MOV R0,R8
\ 000000B6 ........ BL CPU_SR_Restore
296 break;
\ 000000BA 29E0 B.N ??CPU_IntSrcDis_7
297
298
299 /* ---------------- EXTERNAL INTERRUPT ---------------- */
300 default:
301 pos_max = CPU_INT_SRC_POS_MAX;
\ ??CPU_IntSrcDis_6:
\ 000000BC ........ LDR.W R0,??DataTable6_4 ;; 0xe000e004
\ 000000C0 0068 LDR R0,[R0, #+0]
\ 000000C2 401C ADDS R0,R0,#+1
\ 000000C4 10F01F00 ANDS R0,R0,#0x1F
\ 000000C8 4001 LSLS R0,R0,#+5
\ 000000CA 1030 ADDS R0,R0,#+16
\ 000000CC 0600 MOVS R6,R0
302 if (pos < pos_max) { /* See Note #3. */
\ 000000CE E4B2 UXTB R4,R4 ;; ZeroExt R4,R4,#+24,#+24
\ 000000D0 F6B2 UXTB R6,R6 ;; ZeroExt R6,R6,#+24,#+24
\ 000000D2 B442 CMP R4,R6
\ 000000D4 1CD2 BCS.N ??CPU_IntSrcDis_8
303 group = (pos - 16) / 32;
\ 000000D6 E4B2 UXTB R4,R4 ;; ZeroExt R4,R4,#+24,#+24
\ 000000D8 B4F11000 SUBS R0,R4,#+16
\ 000000DC 2021 MOVS R1,#+32
\ 000000DE 90FBF1F0 SDIV R0,R0,R1
\ 000000E2 0500 MOVS R5,R0
304 nbr = (pos - 16) % 32;
\ 000000E4 E4B2 UXTB R4,R4 ;; ZeroExt R4,R4,#+24,#+24
\ 000000E6 B4F11000 SUBS R0,R4,#+16
\ 000000EA 2021 MOVS R1,#+32
\ 000000EC 90FBF1F2 SDIV R2,R0,R1
\ 000000F0 02FB1102 MLS R2,R2,R1,R0
\ 000000F4 1700 MOVS R7,R2
305
306 CPU_CRITICAL_ENTER();
\ 000000F6 ........ BL CPU_SR_Save
\ 000000FA 8046 MOV R8,R0
307 CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
\ 000000FC EDB2 UXTB R5,R5 ;; ZeroExt R5,R5,#+24,#+24
\ 000000FE ........ LDR.W R0,??DataTable6_5 ;; 0xe000e180
\ 00000102 0121 MOVS R1,#+1
\ 00000104 B940 LSLS R1,R1,R7
\ 00000106 40F82510 STR R1,[R0, R5, LSL #+2]
308 CPU_CRITICAL_EXIT();
\ 0000010A 4046 MOV R0,R8
\ 0000010C ........ BL CPU_SR_Restore
309 }
310 break;
311 }
312 }
\ ??CPU_IntSrcDis_8:
\ ??CPU_IntSrcDis_7:
\ 00000110 BDE8F081 POP {R4-R8,PC} ;; return
313
314
315 /*$PAGE*/
316 /*
317 *********************************************************************************************************
318 * CPU_IntSrcEn()
319 *
320 * Description : Enable an interrupt source.
321 *
322 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
323 *
324 * Return(s) : none.
325 *
326 * Caller(s) : Application.
327 *
328 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
329 *
330 * (2) See 'CPU_IntSrcDis() Note #2'.
331 *
332 * (3) See 'CPU_IntSrcDis() Note #3'.
333 *********************************************************************************************************
334 */
335
\ In section .text, align 2, keep-with-next
336 void CPU_IntSrcEn (CPU_INT08U pos)
337 {
\ CPU_IntSrcEn:
\ 00000000 2DE9F041 PUSH {R4-R8,LR}
\ 00000004 0400 MOVS R4,R0
338 CPU_INT08U group;
339 CPU_INT08U nbr;
340 CPU_INT08U pos_max;
341 CPU_SR_ALLOC();
\ 00000006 5FF00008 MOVS R8,#+0
342
343
344 switch (pos) {
\ 0000000A E4B2 UXTB R4,R4 ;; ZeroExt R4,R4,#+24,#+24
\ 0000000C 002C CMP R4,#+0
\ 0000000E 17D0 BEQ.N ??CPU_IntSrcEn_0
\ 00000010 022C CMP R4,#+2
\ 00000012 16D0 BEQ.N ??CPU_IntSrcEn_1
\ 00000014 15D3 BCC.N ??CPU_IntSrcEn_1
\ 00000016 042C CMP R4,#+4
\ 00000018 14D0 BEQ.N ??CPU_IntSrcEn_2
\ 0000001A 12D3 BCC.N ??CPU_IntSrcEn_1
\ 0000001C 062C CMP R4,#+6
\ 0000001E 2FD0 BEQ.N ??CPU_IntSrcEn_3
\ 00000020 1FD3 BCC.N ??CPU_IntSrcEn_4
\ 00000022 082C CMP R4,#+8
\ 00000024 0CD0 BEQ.N ??CPU_IntSrcEn_0
\ 00000026 0BD3 BCC.N ??CPU_IntSrcEn_0
\ 00000028 0A2C CMP R4,#+10
\ 0000002A 09D0 BEQ.N ??CPU_IntSrcEn_0
\ 0000002C 08D3 BCC.N ??CPU_IntSrcEn_0
\ 0000002E 0C2C CMP R4,#+12
\ 00000030 07D0 BEQ.N ??CPU_IntSrcEn_1
\ 00000032 06D3 BCC.N ??CPU_IntSrcEn_1
\ 00000034 0E2C CMP R4,#+14
\ 00000036 04D0 BEQ.N ??CPU_IntSrcEn_1
\ 00000038 02D3 BCC.N ??CPU_IntSrcEn_0
\ 0000003A 0F2C CMP R4,#+15
\ 0000003C 2FD0 BEQ.N ??CPU_IntSrcEn_5
\ 0000003E 3DE0 B.N ??CPU_IntSrcEn_6
345 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
346 case CPU_INT_RSVD_07:
347 case CPU_INT_RSVD_08:
348 case CPU_INT_RSVD_09:
349 case CPU_INT_RSVD_10:
350 case CPU_INT_RSVD_13:
351 break;
\ ??CPU_IntSrcEn_0:
\ 00000040 66E0 B.N ??CPU_IntSrcEn_7
352
353
354 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
355 case CPU_INT_RESET: /* Reset (see Note #2). */
356 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
357 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
358 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
359 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
360 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
361 break;
\ ??CPU_IntSrcEn_1:
\ 00000042 65E0 B.N ??CPU_IntSrcEn_7
362
363 case CPU_INT_MEM: /* Memory management. */
364 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcEn_2:
\ 00000044 ........ BL CPU_SR_Save
\ 00000048 8046 MOV R8,R0
365 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
\ 0000004A ........ LDR.W R0,??DataTable6_2 ;; 0xe000ed24
\ 0000004E 0068 LDR R0,[R0, #+0]
\ 00000050 50F48030 ORRS R0,R0,#0x10000
\ 00000054 ........ LDR.W R1,??DataTable6_2 ;; 0xe000ed24
\ 00000058 0860 STR R0,[R1, #+0]
366 CPU_CRITICAL_EXIT();
\ 0000005A 4046 MOV R0,R8
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