📄 cpu_c.lst
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\ 00000038 B0F18044 SUBS R4,R0,#+1073741824
\ 0000003C C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 0000003E 8D00 LSLS R5,R1,#+2
\ 00000040 15EB4414 ADDS R4,R5,R4, LSL #+5
\ 00000044 2200 MOVS R2,R4
147 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
\ 00000046 12F18444 ADDS R4,R2,#+1107296256
\ 0000004A 2300 MOVS R3,R4
148
149 *(volatile CPU_INT32U *)(bit_word_addr) = 0;
\ 0000004C 0024 MOVS R4,#+0
\ 0000004E 1C60 STR R4,[R3, #+0]
150 }
151 }
\ ??CPU_BitBandClr_1:
\ 00000050 30BC POP {R4,R5}
\ 00000052 7047 BX LR ;; return
152
153
154 /*$PAGE*/
155 /*
156 *********************************************************************************************************
157 * CPU_BitBandSet()
158 *
159 * Description : Set bit in bit-band region.
160 *
161 * Argument(s) : addr Byte address in memory space.
162 *
163 * bit_nbr Bit number in byte.
164 *
165 * Return(s) : none.
166 *
167 * Caller(s) : Application.
168 *
169 * Note(s) : none.
170 *********************************************************************************************************
171 */
172
\ In section .text, align 2, keep-with-next
173 void CPU_BitBandSet (CPU_ADDR addr,
174 CPU_INT08U bit_nbr)
175 {
\ CPU_BitBandSet:
\ 00000000 30B4 PUSH {R4,R5}
176 CPU_ADDR bit_word_off;
177 CPU_ADDR bit_word_addr;
178
179
180 if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
181 (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
\ 00000002 B0F1005F CMP R0,#+536870912
\ 00000006 10D3 BCC.N ??CPU_BitBandSet_0
\ 00000008 ........ LDR.W R4,??DataTable6 ;; 0x20100000
\ 0000000C A042 CMP R0,R4
\ 0000000E 0CD2 BCS.N ??CPU_BitBandSet_0
182 bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
\ 00000010 B0F10054 SUBS R4,R0,#+536870912
\ 00000014 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000016 8D00 LSLS R5,R1,#+2
\ 00000018 15EB4414 ADDS R4,R5,R4, LSL #+5
\ 0000001C 2200 MOVS R2,R4
183 bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
\ 0000001E 12F10854 ADDS R4,R2,#+570425344
\ 00000022 2300 MOVS R3,R4
184
185 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
\ 00000024 0124 MOVS R4,#+1
\ 00000026 1C60 STR R4,[R3, #+0]
\ 00000028 12E0 B.N ??CPU_BitBandSet_1
186
187 } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
188 (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
\ ??CPU_BitBandSet_0:
\ 0000002A B0F1804F CMP R0,#+1073741824
\ 0000002E 0FD3 BCC.N ??CPU_BitBandSet_1
\ 00000030 ........ LDR.W R4,??DataTable6_1 ;; 0x40100000
\ 00000034 A042 CMP R0,R4
\ 00000036 0BD2 BCS.N ??CPU_BitBandSet_1
189 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
\ 00000038 B0F18044 SUBS R4,R0,#+1073741824
\ 0000003C C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 0000003E 8D00 LSLS R5,R1,#+2
\ 00000040 15EB4414 ADDS R4,R5,R4, LSL #+5
\ 00000044 2200 MOVS R2,R4
190 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
\ 00000046 12F18444 ADDS R4,R2,#+1107296256
\ 0000004A 2300 MOVS R3,R4
191
192 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
\ 0000004C 0124 MOVS R4,#+1
\ 0000004E 1C60 STR R4,[R3, #+0]
193 }
194 }
\ ??CPU_BitBandSet_1:
\ 00000050 30BC POP {R4,R5}
\ 00000052 7047 BX LR ;; return
195
196
197 /*$PAGE*/
198 /*
199 *********************************************************************************************************
200 * CPU_IntSrcDis()
201 *
202 * Description : Disable an interrupt source.
203 *
204 * Argument(s) : pos Position of interrupt vector in interrupt table :
205 *
206 * 0 Invalid (see Note #1a).
207 * 1 Invalid (see Note #1b).
208 * 2 Non-maskable interrupt.
209 * 3 Hard Fault.
210 * 4 Memory Management.
211 * 5 Bus Fault.
212 * 6 Usage Fault.
213 * 7-10 Reserved.
214 * 11 SVCall
215 * 12 Debug monitor.
216 * 13 Reserved
217 * 14 PendSV.
218 * 15 SysTick.
219 * 16+ External Interrupt.
220 *
221 * Return(s) : none.
222 *
223 * Caller(s) : Application.
224 *
225 * Note(s) : (1) Several table positions do not contain interrupt sources :
226 *
227 * (a) Position 0 contains the stack pointer.
228 * (b) Positions 7-10, 13 are reserved.
229 *
230 * (2) Several interrupts cannot be disabled/enabled :
231 *
232 * (a) Reset.
233 * (b) NMI.
234 * (c) Hard fault.
235 * (d) SVCall.
236 * (e) Debug monitor.
237 * (f) PendSV.
238 *
239 * (3) The maximum Cortex-M3 table position is 256. A particular Cortex-M3 may have fewer
240 * than 240 external exceptions and, consequently, fewer than 256 table positions.
241 * This function assumes that the specified table position is valid if the interrupt
242 * controller type register's INTLINESNUM field is large enough so that the position
243 * COULD be valid.
244 *********************************************************************************************************
245 */
246 /*$PAGE*/
\ In section .text, align 2, keep-with-next
247 void CPU_IntSrcDis (CPU_INT08U pos)
248 {
\ CPU_IntSrcDis:
\ 00000000 2DE9F041 PUSH {R4-R8,LR}
\ 00000004 0400 MOVS R4,R0
249 CPU_INT08U group;
250 CPU_INT08U pos_max;
251 CPU_INT08U nbr;
252 CPU_SR_ALLOC();
\ 00000006 5FF00008 MOVS R8,#+0
253
254
255 switch (pos) {
\ 0000000A E4B2 UXTB R4,R4 ;; ZeroExt R4,R4,#+24,#+24
\ 0000000C 002C CMP R4,#+0
\ 0000000E 17D0 BEQ.N ??CPU_IntSrcDis_0
\ 00000010 022C CMP R4,#+2
\ 00000012 16D0 BEQ.N ??CPU_IntSrcDis_1
\ 00000014 15D3 BCC.N ??CPU_IntSrcDis_1
\ 00000016 042C CMP R4,#+4
\ 00000018 14D0 BEQ.N ??CPU_IntSrcDis_2
\ 0000001A 12D3 BCC.N ??CPU_IntSrcDis_1
\ 0000001C 062C CMP R4,#+6
\ 0000001E 2FD0 BEQ.N ??CPU_IntSrcDis_3
\ 00000020 1FD3 BCC.N ??CPU_IntSrcDis_4
\ 00000022 082C CMP R4,#+8
\ 00000024 0CD0 BEQ.N ??CPU_IntSrcDis_0
\ 00000026 0BD3 BCC.N ??CPU_IntSrcDis_0
\ 00000028 0A2C CMP R4,#+10
\ 0000002A 09D0 BEQ.N ??CPU_IntSrcDis_0
\ 0000002C 08D3 BCC.N ??CPU_IntSrcDis_0
\ 0000002E 0C2C CMP R4,#+12
\ 00000030 07D0 BEQ.N ??CPU_IntSrcDis_1
\ 00000032 06D3 BCC.N ??CPU_IntSrcDis_1
\ 00000034 0E2C CMP R4,#+14
\ 00000036 04D0 BEQ.N ??CPU_IntSrcDis_1
\ 00000038 02D3 BCC.N ??CPU_IntSrcDis_0
\ 0000003A 0F2C CMP R4,#+15
\ 0000003C 2FD0 BEQ.N ??CPU_IntSrcDis_5
\ 0000003E 3DE0 B.N ??CPU_IntSrcDis_6
256 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
257 case CPU_INT_RSVD_07:
258 case CPU_INT_RSVD_08:
259 case CPU_INT_RSVD_09:
260 case CPU_INT_RSVD_10:
261 case CPU_INT_RSVD_13:
262 break;
\ ??CPU_IntSrcDis_0:
\ 00000040 66E0 B.N ??CPU_IntSrcDis_7
263
264
265 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
266 case CPU_INT_RESET: /* Reset (see Note #2). */
267 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
268 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
269 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
270 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
271 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
272 break;
\ ??CPU_IntSrcDis_1:
\ 00000042 65E0 B.N ??CPU_IntSrcDis_7
273
274 case CPU_INT_MEM: /* Memory management. */
275 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_2:
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