📄 cpu_c.lst
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###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.2.52244/W32 for ARM 07/Aug/2011 12:10:24 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = F:\stm32\我的程序\Micrium\Software\uC-CPU\ARM-Cortex-M3\ #
# IAR\cpu_c.c #
# Command line = F:\stm32\我的程序\Micrium\Software\uC-CPU\ARM-Cortex-M3\ #
# IAR\cpu_c.c -D USE_STDPERIPH_DRIVER -D STM32F10X_CL #
# -lCN F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flas #
# h\List\ -o F:\stm32\我的程序\Micrium\Software\EWARM\OS-I #
# I\Flash\Obj\ --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian=little --cpu=Cortex-M3 #
# -e --fpu=None --dlib_config #
# D:\arm\INC\c\DLib_Config_Normal.h -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\APP\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ #
# -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP #
# \ST\CMSIS\CM3\CoreSupport\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \CMSIS\CM3\DeviceSupport\ST\STM32F10x\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \STM32F10x_StdPeriph_Driver\inc\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\uC #
# OS-II\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II #
# \..\..\uCOS-II\Ports\ARM-Cortex-M3\Generic\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uCO #
# S-II\Source\ -I F:\stm32\我的程序\Micrium\Software\EWARM #
# \OS-II\..\..\uC-LIB\ -I F:\stm32\我的程序\Micrium\Softwa #
# re\EWARM\OS-II\..\..\uC-LIB\Ports\ARM-Cortex-M3\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uC- #
# CPU\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\. #
# .\..\uC-CPU\ARM-Cortex-M3\IAR\ -On --use_c++_inline #
# List file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\cpu_c.lst #
# Object file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Obj #
# \cpu_c.o #
# #
# #
###############################################################################
F:\stm32\我的程序\Micrium\Software\uC-CPU\ARM-Cortex-M3\IAR\cpu_c.c
1 /*
2 *********************************************************************************************************
3 * uC/CPU
4 * CPU CONFIGURATION & PORT LAYER
5 *
6 * (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
7 *
8 * All rights reserved. Protected by international copyright laws.
9 *
10 * uC/CPU is provided in source form to registered licensees ONLY. It is
11 * illegal to distribute this source code to any third party unless you receive
12 * written permission by an authorized Micrium representative. Knowledge of
13 * the source code may NOT be used to develop a similar product.
14 *
15 * Please help us continue to provide the Embedded community with the finest
16 * software available. Your honesty is greatly appreciated.
17 *
18 * You can contact us at www.micrium.com.
19 *********************************************************************************************************
20 */
21
22 /*
23 *********************************************************************************************************
24 *
25 * CPU PORT FILE
26 *
27 * ARM-Cortex-M3
28 * IAR C Compiler
29 *
30 * Filename : cpu_c.c
31 * Version : V1.28.00.00
32 * Programmer(s) : JJL
33 * BAN
34 *********************************************************************************************************
35 */
36
37
38 /*
39 *********************************************************************************************************
40 * INCLUDE FILES
41 *********************************************************************************************************
42 */
43
44 #include <cpu.h>
45 #include <cpu_core.h>
46
47 #include <lib_def.h>
48
49
50 /*$PAGE*/
51 /*
52 *********************************************************************************************************
53 * LOCAL DEFINES
54 *********************************************************************************************************
55 */
56
57 #define CPU_INT_SRC_POS_MAX ((((CPU_REG_NVIC_NVIC + 1) & 0x1F) * 32) + 16)
58
59 #define CPU_BIT_BAND_SRAM_REG_LO 0x20000000
60 #define CPU_BIT_BAND_SRAM_REG_HI 0x200FFFFF
61 #define CPU_BIT_BAND_SRAM_BASE 0x22000000
62
63
64 #define CPU_BIT_BAND_PERIPH_REG_LO 0x40000000
65 #define CPU_BIT_BAND_PERIPH_REG_HI 0x400FFFFF
66 #define CPU_BIT_BAND_PERIPH_BASE 0x42000000
67
68
69 /*
70 *********************************************************************************************************
71 * LOCAL CONSTANTS
72 *********************************************************************************************************
73 */
74
75
76 /*
77 *********************************************************************************************************
78 * LOCAL DATA TYPES
79 *********************************************************************************************************
80 */
81
82
83 /*
84 *********************************************************************************************************
85 * LOCAL TABLES
86 *********************************************************************************************************
87 */
88
89
90 /*
91 *********************************************************************************************************
92 * LOCAL GLOBAL VARIABLES
93 *********************************************************************************************************
94 */
95
96
97 /*
98 *********************************************************************************************************
99 * LOCAL FUNCTION PROTOTYPES
100 *********************************************************************************************************
101 */
102
103
104 /*
105 *********************************************************************************************************
106 * LOCAL CONFIGURATION ERRORS
107 *********************************************************************************************************
108 */
109
110
111 /*$PAGE*/
112 /*
113 *********************************************************************************************************
114 * CPU_BitBandClr()
115 *
116 * Description : Clear bit in bit-band region.
117 *
118 * Argument(s) : addr Byte address in memory space.
119 *
120 * bit_nbr Bit number in byte.
121 *
122 * Return(s) : none.
123 *
124 * Caller(s) : Application.
125 *
126 * Note(s) : none.
127 *********************************************************************************************************
128 */
129
\ In section .text, align 2, keep-with-next
130 void CPU_BitBandClr (CPU_ADDR addr,
131 CPU_INT08U bit_nbr)
132 {
\ CPU_BitBandClr:
\ 00000000 30B4 PUSH {R4,R5}
133 CPU_ADDR bit_word_off;
134 CPU_ADDR bit_word_addr;
135
136
137 if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
138 (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
\ 00000002 B0F1005F CMP R0,#+536870912
\ 00000006 10D3 BCC.N ??CPU_BitBandClr_0
\ 00000008 ........ LDR.W R4,??DataTable6 ;; 0x20100000
\ 0000000C A042 CMP R0,R4
\ 0000000E 0CD2 BCS.N ??CPU_BitBandClr_0
139 bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
\ 00000010 B0F10054 SUBS R4,R0,#+536870912
\ 00000014 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000016 8D00 LSLS R5,R1,#+2
\ 00000018 15EB4414 ADDS R4,R5,R4, LSL #+5
\ 0000001C 2200 MOVS R2,R4
140 bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
\ 0000001E 12F10854 ADDS R4,R2,#+570425344
\ 00000022 2300 MOVS R3,R4
141
142 *(volatile CPU_INT32U *)(bit_word_addr) = 0;
\ 00000024 0024 MOVS R4,#+0
\ 00000026 1C60 STR R4,[R3, #+0]
\ 00000028 12E0 B.N ??CPU_BitBandClr_1
143
144 } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
145 (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
\ ??CPU_BitBandClr_0:
\ 0000002A B0F1804F CMP R0,#+1073741824
\ 0000002E 0FD3 BCC.N ??CPU_BitBandClr_1
\ 00000030 ........ LDR.W R4,??DataTable6_1 ;; 0x40100000
\ 00000034 A042 CMP R0,R4
\ 00000036 0BD2 BCS.N ??CPU_BitBandClr_1
146 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
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