📄 bsp_i2c.c
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if (nbr_bytes < 2) {
return (DEF_FAIL);
}
err = BSP_I2C_StartXfer(i2c_id,
i2c_addr,
BSP_I2C_ACCESS_TYPE_WR_RD,
p_buf,
nbr_bytes);
return (err);
}
/*
*********************************************************************************************************
* BSP_I2C1_EventISR_Handle()
* BSP_I2C2_EventISR_Handle
*
* Description : I2C1/I2C2 ISR handlers
*
* Argument(s) : none.
*
* Return(s) : none.
*
* Caller(s) : This is an ISR.
*
* Note(s) : none.
*********************************************************************************************************
*/
static void BSP_I2C1_EventISR_Handler (void)
{
BSP_I2Cx_EventISR_Handler(0);
}
static void BSP_I2C2_EventISR_Handler (void)
{
BSP_I2Cx_EventISR_Handler(1);
}
/*
*********************************************************************************************************
* BSP_I2Cx_EventISR_Handler()
*
* Description : Generic ISR events handler
*
* Argument(s) : i2c_nbr I2C peripheral number.
* 0 I2C1 peripheral
* 1 I2C2 peripheral
*
* Return(s) : none.
*
* Caller(s) : BSP_I2C1_EventISR_Handler()
* BSP_I2C2_EventISR_Handler()
*
* Note(s) : none.
*********************************************************************************************************
*/
void BSP_I2Cx_EventISR_Handler (CPU_INT08U i2c_nbr)
{
BSP_I2C_DEV_STATUS *p_i2c_dev_status;
BSP_I2C_REG *p_i2c_reg;
CPU_INT32U int_stat1;
CPU_INT32U int_stat2;
switch (i2c_nbr) {
case 0:
p_i2c_reg = (BSP_I2C_REG *)BSP_I2C_REG_I2C1_BASE_ADDR;
break;
case 1:
p_i2c_reg = (BSP_I2C_REG *)BSP_I2C_REG_I2C2_BASE_ADDR;
break;
default:
break;
}
p_i2c_dev_status = (BSP_I2C_DEV_STATUS *)&BSP_I2C_DevTbl[i2c_nbr];
int_stat1 = p_i2c_reg->I2C_SR1;
int_stat1 &= BSP_I2C_REG_SR1_EVENT_MASK;
switch (p_i2c_dev_status->State) {
case BSP_I2C_STATE_START: /* --------------- I2C START STATE ------------------ */
/* If the start bit flag has been generated ... */
if (DEF_BIT_IS_SET(int_stat1, BSP_I2C_REG_SR1_SB)) {
/* Send the Address with the correct direction */
if (p_i2c_dev_status->AccessType == BSP_I2C_ACCESS_TYPE_RD) {
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_ACK);
p_i2c_reg->I2C_DR = (p_i2c_dev_status->Addr << 1)
| DEF_BIT_00;
} else {
p_i2c_reg->I2C_DR = (p_i2c_dev_status->Addr << 1) & DEF_BIT_FIELD(7, 1);
}
p_i2c_dev_status->State = BSP_I2C_STATE_ADDR;
}
break;
case BSP_I2C_STATE_ADDR: /* --------------- I2C ADRESS STATE ----------------- */
/* If the address was sent ... */
if (DEF_BIT_IS_SET(int_stat1, BSP_I2C_REG_SR1_ADDR)) {
int_stat2 = p_i2c_reg->I2C_SR2;
(void)&int_stat2;
switch (p_i2c_dev_status->AccessType) {
case BSP_I2C_ACCESS_TYPE_RD:
if (p_i2c_dev_status->BufLen == 1) {
p_i2c_dev_status->State = BSP_I2C_STATE_STOP;
DEF_BIT_CLR(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_ACK);
} else {
p_i2c_dev_status->State = BSP_I2C_STATE_DATA;
}
break;
case BSP_I2C_ACCESS_TYPE_WR:
case BSP_I2C_ACCESS_TYPE_WR_RD:
if (DEF_BIT_IS_SET(int_stat1, BSP_I2C_REG_SR1_TXE)) {
p_i2c_reg->I2C_DR = (CPU_INT32U)(*(p_i2c_dev_status->BufPtr));
p_i2c_dev_status->BufPtr++;
p_i2c_dev_status->BufLen--;
if (p_i2c_dev_status->BufLen == 0) {
p_i2c_dev_status->State = BSP_I2C_STATE_STOP;
} else {
p_i2c_dev_status->State = BSP_I2C_STATE_DATA;
}
}
break;
default:
break;
}
} else {
p_i2c_dev_status->State = BSP_I2C_STATE_IDLE;
p_i2c_dev_status->AccessType = BSP_I2C_ACCESS_TYPE_NONE;
DEF_BIT_CLR(p_i2c_reg->I2C_CR2, BSP_I2C_REG_CR2_ITEVTEN |
BSP_I2C_REG_CR2_ITERREN);
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_STOP);
BSP_OS_SemPost(&(p_i2c_dev_status->SemWait));
}
break;
case BSP_I2C_STATE_DATA: /* ---------------- I2C DATA STATE ------------------ */
switch (p_i2c_dev_status->AccessType) {
/* If the I2C is receiving ... */
case BSP_I2C_ACCESS_TYPE_WR_RD:
if (DEF_BIT_IS_SET(int_stat1, BSP_I2C_REG_SR1_TXE)) {
/* Initialize the Transfer as read access */
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_START);
p_i2c_dev_status->State = BSP_I2C_STATE_START;
p_i2c_dev_status->AccessType = BSP_I2C_ACCESS_TYPE_RD;
}
break;
case BSP_I2C_ACCESS_TYPE_RD:
/* If the receive register is not empty */
if (DEF_BIT_IS_SET(int_stat1, BSP_I2C_REG_SR1_RXNE)) {
*(p_i2c_dev_status->BufPtr) = (CPU_INT08U)(p_i2c_reg->I2C_DR & BSP_I2C_REG_DR_MASK);
p_i2c_dev_status->BufPtr++;
p_i2c_dev_status->BufLen--;
/* If it is the last byte */
if (p_i2c_dev_status->BufLen == 1) {
/* NOT Acknowledge, Generate STOP condition */
DEF_BIT_CLR(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_ACK);
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_STOP);
p_i2c_dev_status->State = BSP_I2C_STATE_STOP;
}
}
break;
case BSP_I2C_ACCESS_TYPE_WR:
if (DEF_BIT_IS_SET(int_stat1, BSP_I2C_REG_SR1_TXE)) {
p_i2c_reg->I2C_DR = (CPU_INT32U)(*(p_i2c_dev_status->BufPtr));
p_i2c_dev_status->BufPtr++;
p_i2c_dev_status->BufLen--;
if (p_i2c_dev_status->BufLen == 0) {
p_i2c_dev_status->State = BSP_I2C_STATE_STOP;
}
}
break;
}
break;
case BSP_I2C_STATE_STOP: /* ---------------- I2C STOP STATE ------------------ */
if (DEF_BIT_IS_SET(int_stat1, BSP_I2C_REG_SR1_BTF)) {
switch (p_i2c_dev_status->AccessType) {
case BSP_I2C_ACCESS_TYPE_WR_RD:
case BSP_I2C_ACCESS_TYPE_RD:
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_STOP);
*(p_i2c_dev_status->BufPtr) = (CPU_INT08U)(p_i2c_reg->I2C_DR & BSP_I2C_REG_DR_MASK);;
p_i2c_dev_status->BufPtr++;
p_i2c_dev_status->BufLen--;
break;
case BSP_I2C_ACCESS_TYPE_WR:
DEF_BIT_CLR(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_ACK);
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_STOP);
break;
}
p_i2c_dev_status->State = BSP_I2C_STATE_IDLE;
p_i2c_dev_status->AccessType = BSP_I2C_ACCESS_TYPE_NONE;
DEF_BIT_CLR(p_i2c_reg->I2C_CR2, BSP_I2C_REG_CR2_ITEVTEN |
BSP_I2C_REG_CR2_ITERREN);
BSP_OS_SemPost(&(p_i2c_dev_status->SemWait));
}
break;
case BSP_I2C_STATE_IDLE:
default:
break;
}
}
/*
*********************************************************************************************************
* BSP_I2Cx_EventISR_Handler()
*
* Description : Generic ISR events handler
*
* Argument(s) : i2c_nbr I2C peripheral number.
* 0 I2C1 peripheral
* 1 I2C2 peripheral
*
* Return(s) : none.
*
* Caller(s) : BSP_I2C1_EventISR_Handler()
* BSP_I2C2_EventISR_Handler()
*
* Note(s) : none.
*********************************************************************************************************
*/
static void BSP_I2C1_ErrISR_Handler (void)
{
BSP_I2Cx_ErrISR_Handler(0);
}
static void BSP_I2C2_ErrISR_Handler (void)
{
BSP_I2Cx_ErrISR_Handler(1);
}
/*
*********************************************************************************************************
* BSP_I2Cx_ErrISR_Handler()
*
* Description : Generic ISR errors handler
*
* Argument(s) : i2c_nbr I2C peripheral number.
* 0 I2C1 peripheral
* 1 I2C2 peripheral
*
* Return(s) : none.
*
* Caller(s) : BSP_I2C1_ErrISR_Handler()
* BSP_I2C2_ErrISR_Handler()
*
* Note(s) : none
*********************************************************************************************************
*/
static void BSP_I2Cx_ErrISR_Handler (CPU_INT08U i2c_nbr)
{
BSP_I2C_DEV_STATUS *p_i2c_dev_status;
BSP_I2C_REG *p_i2c_reg;
CPU_INT32U int_stat1;
switch (i2c_nbr) {
case 0:
p_i2c_reg = (BSP_I2C_REG *)BSP_I2C_REG_I2C1_BASE_ADDR;
break;
case 1:
p_i2c_reg = (BSP_I2C_REG *)BSP_I2C_REG_I2C2_BASE_ADDR;
break;
default:
break;
}
p_i2c_dev_status = (BSP_I2C_DEV_STATUS *)&BSP_I2C_DevTbl[i2c_nbr];
int_stat1 = p_i2c_reg->I2C_SR1;
int_stat1 &= BSP_I2C_REG_SR1_ERR_MASK;
DEF_BIT_CLR(p_i2c_reg->I2C_SR1, int_stat1);
if (p_i2c_dev_status->State != BSP_I2C_STATE_IDLE) {
p_i2c_dev_status->State = BSP_I2C_STATE_IDLE;
p_i2c_dev_status->AccessType = BSP_I2C_ACCESS_TYPE_NONE;
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_STOP);
DEF_BIT_CLR(p_i2c_reg->I2C_CR2, (BSP_I2C_REG_CR2_ITEVTEN |
BSP_I2C_REG_CR2_ITERREN));
BSP_OS_SemPost(&(p_i2c_dev_status->SemWait));
}
}
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