📄 bsp_i2c.c
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RCC_GetClocksFreq(&rcc_clocks);
pclk_freq = rcc_clocks.PCLK1_Frequency;
if (pclk_freq > BSP_I2C_PER_CLK_MAX_FREQ_HZ) {
return (DEF_FAIL);
}
p_i2c_reg->I2C_CR1 = BSP_I2C_REG_CR1_SWRST; /* Perform a software reset */
p_i2c_reg->I2C_CR1 = DEF_BIT_NONE;
/* Set the frequency range */
p_i2c_reg->I2C_CR2 = (pclk_freq / DEF_TIME_NBR_uS_PER_SEC)
& BSP_I2C_REG_CR2_FREQ_MASK;
/* Calculate the clock divider */
switch (i2c_mode) {
case BSP_I2C_MODE_STANDARD:
if (clk_freq > BSP_I2C_MODE_STANDARD_MAX_FREQ_HZ) {
return (DEF_FAIL);
}
reg_val = (((2 * pclk_freq + clk_freq)/ (2 * clk_freq)) / 2)
& BSP_I2C_REG_CCR_MASK;
break;
case BSP_I2C_MODE_FAST_1_2:
if (clk_freq > BSP_I2C_MODE_FAST_MAX_FREQ_HZ) {
return (DEF_FAIL);
}
DEF_BIT_SET(reg_val, BSP_I2C_REG_CCR_FS);
reg_val = (((2 * pclk_freq + clk_freq)/ (2 * clk_freq)) / 3)
& BSP_I2C_REG_CCR_MASK;
break;
case BSP_I2C_MODE_FAST_16_9:
if (clk_freq > BSP_I2C_MODE_FAST_MAX_FREQ_HZ) {
return (DEF_FAIL);
}
reg_val = (((2 * pclk_freq) + (25 * clk_freq)) / (50 * clk_freq))
& BSP_I2C_REG_CCR_MASK;
DEF_BIT_SET(reg_val, BSP_I2C_REG_CCR_DUTY | BSP_I2C_REG_CCR_FS);
break;
}
p_i2c_reg->I2C_CCR = reg_val;
/* Enable interrupts in the interrupt controller */
switch (i2c_id) {
case BSP_I2C_ID_I2C1:
BSP_IntVectSet(BSP_INT_ID_I2C1_EV, BSP_I2C1_EventISR_Handler);
BSP_IntEn(BSP_INT_ID_I2C1_EV);
BSP_IntVectSet(BSP_INT_ID_I2C1_ER, BSP_I2C1_ErrISR_Handler);
BSP_IntEn(BSP_INT_ID_I2C1_ER);
break;
case BSP_I2C_ID_I2C2:
BSP_IntVectSet(BSP_INT_ID_I2C2_EV, BSP_I2C2_EventISR_Handler);
BSP_IntEn(BSP_INT_ID_I2C2_EV);
BSP_IntVectSet(BSP_INT_ID_I2C2_ER, BSP_I2C2_ErrISR_Handler);
BSP_IntEn(BSP_INT_ID_I2C1_ER);
break;
default:
break;
}
/* Initialize the device status */
p_i2c_dev_status->Addr = DEF_BIT_NONE;
p_i2c_dev_status->AccessType = BSP_I2C_ACCESS_TYPE_NONE;
p_i2c_dev_status->State = BSP_I2C_STATE_IDLE;
p_i2c_dev_status->BufPtr = (CPU_INT08U *)0;
p_i2c_dev_status->BufLen = 0;
p_i2c_reg->I2C_CR1 = BSP_I2C_REG_CR1_PE; /* Enable the I2C peripheral */
return (DEF_OK);
}
/*
*********************************************************************************************************
* BSP_I2C_StartXfer()
*
* Description : Initialize and Start a new transfer in the I2C bus.
*
* Argument(s) : i2c_id I2C peripheral ID
* BSP_I2C_ID_I2C1
* BSP_I2C_ID_I2C2
*
* i2c_addr The I2C device address
*
* i2c_acess_type I2C Access Type
* BSP_I2C_ACCESS_TYPE_RD
* BSP_I2C_ACCESS_TYPE_WR
* BSP_I2C_ACCESS_TYPE_WR_RD
*
* p_buf Pointer to the buffer into which the bytes will be stored.
*
* nbr_bytes Number of bytes to read.
*
* Return(s) : DEF_OK If the transfer could be initialized and started
* DEF_FAIL If the transfer could no bet initialized and started
*
* Caller(s) : BSP_I2C_Rd()
* BSP_I2C_Wr()
* BSP_I2C_WrRd()
*
* Note(s) : none.
*********************************************************************************************************
*/
static CPU_BOOLEAN BSP_I2C_StartXfer (CPU_INT08U i2c_id,
CPU_INT08U i2c_addr,
CPU_INT08U i2c_access_type,
CPU_INT08U *p_buf,
CPU_INT08U nbr_bytes)
{
CPU_BOOLEAN err;
BSP_I2C_DEV_STATUS *p_i2c_dev_status;
BSP_I2C_REG *p_i2c_reg;
err = DEF_OK;
switch (i2c_id) {
case BSP_I2C_ID_I2C1:
p_i2c_reg = (BSP_I2C_REG *)BSP_I2C_REG_I2C1_BASE_ADDR;
p_i2c_dev_status = (BSP_I2C_DEV_STATUS *)&BSP_I2C_DevTbl[0];
break;
case BSP_I2C_ID_I2C2:
p_i2c_reg = (BSP_I2C_REG *)BSP_I2C_REG_I2C2_BASE_ADDR;
p_i2c_dev_status = (BSP_I2C_DEV_STATUS *)&BSP_I2C_DevTbl[1];
break;
default:
return (DEF_FAIL);
}
err = BSP_OS_SemWait(&(p_i2c_dev_status->SemLock), /* Lock the I2C peripheral */
0);
if (err == DEF_FAIL) {
return (DEF_FAIL);
}
/* Initialize the device structure */
p_i2c_dev_status->Addr = (i2c_addr); /* I2C Slave address */
p_i2c_dev_status->AccessType = i2c_access_type; /* Set the access type */
p_i2c_dev_status->State = BSP_I2C_STATE_START; /* Set the START state */
p_i2c_dev_status->BufPtr = p_buf; /* Set the buffer information */
p_i2c_dev_status->BufLen = nbr_bytes;
DEF_BIT_SET(p_i2c_reg->I2C_CR1, BSP_I2C_REG_CR1_START); /* Generate the start condition */
DEF_BIT_SET(p_i2c_reg->I2C_CR2, BSP_I2C_REG_CR2_ITEVTEN | /* Enable Bus Errors and bus Events interrupts */
BSP_I2C_REG_CR2_ITERREN);
/* Wait until the transfer completes */
err = BSP_OS_SemWait(&(p_i2c_dev_status->SemWait),
500);
BSP_OS_SemPost(&(p_i2c_dev_status->SemLock)); /* Release the I2C Peripheral */
if (p_i2c_dev_status->BufLen != 0) { /* If the transfer is incomplete ... */
err = DEF_FAIL; /* ... return an errror */
}
return (err);
}
/*
*********************************************************************************************************
* BSP_I2C_Rd()
*
* Description : Read 'n' bytes from the I2C bus.
*
* Argument(s) : i2c_nbr I2C peripheral number
* BSP_I2C_ID_I2C1
* BSP_I2C_ID_I2C2
*
* i2c_addr The I2C device address
*
* p_buf Pointer to the buffer into which the bytes will be stored.
*
* nbr_bytes Number of bytes to be read.
*
* Return(s) : DEF_OK If all bytes were read.
* DEF_FAIL If all bytes could not be read.
*
* Caller(s) : Application
*
* Note(s) : none.
*********************************************************************************************************
*/
CPU_BOOLEAN BSP_I2C_Rd (CPU_INT08U i2c_id,
CPU_INT08U i2c_addr,
CPU_INT08U *p_buf,
CPU_INT08U nbr_bytes)
{
CPU_BOOLEAN err;
if (p_buf == (CPU_INT08U *)0) {
return (DEF_FAIL);
}
if (nbr_bytes < 1) {
return (DEF_FAIL);
}
err = BSP_I2C_StartXfer(i2c_id,
i2c_addr,
BSP_I2C_ACCESS_TYPE_RD,
p_buf,
nbr_bytes);
return (err);
}
/*
*********************************************************************************************************
* BSP_I2C_Wr()
*
* Description : Write 'n' bytes tothe I2C bus.
*
* Argument(s) : i2c_nbr I2C peripheral number
* BSP_I2C_ID_I2C1
* BSP_I2C_ID_I2C2
*
* i2c_addr The I2C device address
*
* p_buf Pointer to the buffer where the bytes will be transfered.
*
* nbr_bytes Number of bytes to be read.
*
* Return(s) : DEF_OK If all bytes were written
* DEF_FAIL If all bytes could not be written.
*
* Caller(s) : Application
*
* Note(s) : none.
*********************************************************************************************************
*/
CPU_BOOLEAN BSP_I2C_Wr (CPU_INT08U i2c_id,
CPU_INT08U i2c_addr,
CPU_INT08U *p_buf,
CPU_INT08U nbr_bytes)
{
CPU_BOOLEAN err;
if (p_buf == (CPU_INT08U *)0) {
return (DEF_FAIL);
}
if (nbr_bytes < 1) {
return (DEF_FAIL);
}
err = BSP_I2C_StartXfer(i2c_id,
i2c_addr,
BSP_I2C_ACCESS_TYPE_WR,
p_buf,
nbr_bytes);
return (err);
}
/*
*********************************************************************************************************
* BSP_I2C_WrRd()
*
* Description : Perform a write followed by multiples/single read(s)
*
* Argument(s) : i2c_nbr I2C peripheral number
* BSP_I2C_ID_I2C1
* BSP_I2C_ID_I2C2
*
* i2c_addr The I2C device address
*
* p_buf Pointer to the buffer where the bytes will be transfered/received.
*
* nbr_bytes Number of bytes to be read.
*
* Return(s) : DEF_OK If all bytes were read
* DEF_FAIL If all bytes could not be read.
*
* Caller(s) : Application
*
* Note(s) : none.
*********************************************************************************************************
*/
CPU_BOOLEAN BSP_I2C_WrRd (CPU_INT08U i2c_id,
CPU_INT08U i2c_addr,
CPU_INT08U *p_buf,
CPU_INT08U nbr_bytes)
{
CPU_BOOLEAN err;
if (p_buf == (CPU_INT08U *)0) {
return (DEF_FAIL);
}
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