f2407_c.h

一个简单明了的电压空间矢量pwm程序

//T3CNT .set 7501h //; GP Timer 3 counter register
#define T3CNT (*(volatile unsigned int*) 0x7501)
//T3CMPR .set 7502h //; GP Timer 3 compare register
#define T3CMPR (*(volatile unsigned int*) 0x7502)
//T3PR .set 7503h //; GP Timer 3 period register
#define T3PR (*(volatile unsigned int*) 0x7503)
//T3CON .set 7504h //; GP Timer 3 control register
#define T3CON (*(volatile unsigned int*) 0x7504)
//T4CNT .set 7505h //; GP Timer 4 counter register
#define T4CNT (*(volatile unsigned int*) 0x7505)
//T4CMPR .set 7506h //; GP Timer 4 compare register
#define T4CMPR (*(volatile unsigned int*) 0x7506)
//T4PR .set 7507h //; GP Timer 4 period register
#define T4PR (*(volatile unsigned int*) 0x7507)
//T4CON .set 7508h //; GP Timer 4 control register
#define T4CON (*(volatile unsigned int*) 0x7508)
//COMCONB .set 7511h //; Compare control register B
#define COMCONB (*(volatile unsigned int*) 0x7511)
//ACTRB .set 7513h //; Full compare Action control register B
#define ACTRB (*(volatile unsigned int*) 0x7513)
//DBTCONB .set 7515h //; Dead-band timer control register B
#define DBTCONB (*(volatile unsigned int*) 0x7515)
//CMPR4 .set 7517h //; Full compare unit compare register4
#define CMPR4 (*(volatile unsigned int*) 0x7517)
//CMPR5 .set 7518h //; Full compare unit compare register5
#define CMPR5 (*(volatile unsigned int*) 0x7518)
//CMPR6 .set 7519h //; Full compare unit compare register6
#define CMPR6 (*(volatile unsigned int*) 0x7519)
//CAPCONB .set 7520h //; Capture control register B
#define CAPCONB (*(volatile unsigned int*) 0x7520)
//CAPFIFOB .set 7522h //; Capture FIFO status register B
#define CAPFIFOB (*(volatile unsigned int*) 0x7522)
//CAP4FIFO .set 7523h //; Capture Channel 4 FIFO Top
#define CAP4FIFO (*(volatile unsigned int*) 0x7523)
//CAP5FIFO .set 7524h //; Capture Channel 5 FIFO Top
#define CAP5FIFO (*(volatile unsigned int*) 0x7524)
//CAP6FIFO .set 7525h //; Capture Channel 6 FIFO Top
#define CAP6FIFO (*(volatile unsigned int*) 0x7525)
//CAP4FBOT .set 7527h //; Bottom reg. of capture FIFO stack 4
#define CAP4FBOT (*(volatile unsigned int*) 0x7527)
//CAP5FBOT .set 7528h //; Bottom reg. of capture FIFO stack 5
#define CAP5FBOT (*(volatile unsigned int*) 0x7528)
//CAP6FBOT .set 7529h //; Bottom reg. of capture FIFO stack 6
#define CAP6FBOT (*(volatile unsigned int*) 0x7529)
//EVBIMRA .set 752Ch //; Group A Interrupt Mask Register
#define EVBIMRA (*(volatile unsigned int*) 0x752C)
//EVBIMRB .set 752Dh //; Group B Interrupt Mask Register
#define EVBIMRB (*(volatile unsigned int*) 0x752D)
//EVBIMRC .set 752Eh //; Group C Interrupt Mask Register
#define EVBIMRC (*(volatile unsigned int*) 0x752E)
//EVBIFRA .set 752Fh //; Group A Interrupt Flag Register
#define EVBIFRA (*(volatile unsigned int*) 0x752F)
//EVBIFRB .set 7530h //; Group B Interrupt Flag Register
#define EVBIFRB (*(volatile unsigned int*) 0x7530)
//EVBIFRC .set 7531h //; Group C Interrupt Flag Register
#define EVBIFRC (*(volatile unsigned int*) 0x7531)

//; CAN registers
//CANMDER .set 7100h //; CAN Mailbox Direction/Enable register
#define CANMDER (*(volatile unsigned int*) 0x7100)
//CANTCR .set 7101h //; CAN Transmission Control register
#define CANTCR (*(volatile unsigned int*) 0x7101)
//CANRCR .set 7102h //; CAN Recieve Control register
#define CANRCR (*(volatile unsigned int*) 0x7102)
//CANMCR .set 7103h //; CAN Master Control register
#define CANMCR (*(volatile unsigned int*) 0x7103)
//CANBCR2 .set 7104h //; CAN Bit Config register 2
#define CANBCR2 (*(volatile unsigned int*) 0x7104)
//CANBCR1 .set 7105h //; CAN Bit Config register 1
#define CANBCR1 (*(volatile unsigned int*) 0x7105)
//CANESR .set 7106h //; CAN Error Status register
#define CANESR (*(volatile unsigned int*) 0x7106)
//CANGSR .set 7107h //; CAN Global Status register
#define CANGSR (*(volatile unsigned int*) 0x7107)
//CANCEC .set 7108h //; CAN Trans and Rcv Err counters
#define CANCEC (*(volatile unsigned int*) 0x7108)
//CANIFR .set 7109h //; CAN Interrupt Flag Register
#define CANIFR (*(volatile unsigned int*) 0x7109)
//CANIMR .set 710ah //; CAN Interrupt Mask Register
#define CANIMR (*(volatile unsigned int*) 0x710a)
//CANLAM0H .set 710bh //; CAN Local Acceptance Mask MBX0/1
#define CANLAM0_H (*(volatile unsigned int*) 0x710b)
//CANLAM0L .set 710ch //; CAN Local Acceptance Mask MBX0/1
#define CANLAM0_L (*(volatile unsigned int*) 0x710c)
//CANLAM1H .set 710dh //; CAN Local Acceptance Mask MBX2/3
#define CANLAM1_H (*(volatile unsigned int*) 0x710d)
//CANLAM1L .set 710eh //; CAN Local Acceptance Mask MBX2/3
#define CANLAM1_L (*(volatile unsigned int*) 0x710e)
//CANMSGID0L .set 7200h //; CAN Message ID for mailbox 0 (lower 16 bits)
#define CANMSGID0L (*(volatile unsigned int*) 0x7200)
//CANMSGID0H .set 7201h //; CAN Message ID for mailbox 0 (upper 16 bits)
#define CANMSGID0H (*(volatile unsigned int*) 0x7201)
//CANMSGCTRL0 .set 7202h //; CAN RTR and DLC
#define CANMSGCTRL0 (*(volatile unsigned int*) 0x7202)
//CANMBX0A .set 7204h //; CAN 2 of 8 bytes of Mailbox 0
#define CANMBX0A (*(volatile unsigned int*) 0x7204)
//CANMBX0B .set 7205h //; CAN 2 of 8 bytes of Mailbox 0
#define CANMBX0B (*(volatile unsigned int*) 0x7205)
//CANMBX0C .set 7206h //; CAN 2 of 8 bytes of Mailbox 0
#define CANMBX0C (*(volatile unsigned int*) 0x7206)
//CANMBX0D .set 7207h //; CAN 2 of 8 bytes of Mailbox 0
#define CANMBX0D (*(volatile unsigned int*) 0x7207)
//CANMSGID1L .set 7208h //; CAN Message ID for mailbox 1 (lower 16 bits)
#define CANMSGID1L (*(volatile unsigned int*) 0x7208)
//CANMSGID1H .set 7209h //; CAN Message ID for mailbox 1 (upper 16 bits)
#define CANMSGID1H (*(volatile unsigned int*) 0x7209)
//CANMSGCTRL1 .set 720Ah //; CAN RTR and DLC
#define CANMSGCTRL1 (*(volatile unsigned int*) 0x720a)
//CANMBX1A .set 720Ch //; CAN 2 of 8 bytes of Mailbox 1
#define CANMBX1A (*(volatile unsigned int*) 0x720c)
//CANMBX1B .set 720Dh //; CAN 2 of 8 bytes of Mailbox 1
#define CANMBX1B (*(volatile unsigned int*) 0x720d)
//CANMBX1C .set 720Eh //; CAN 2 of 8 bytes of Mailbox 1
#define CANMBX1C (*(volatile unsigned int*) 0x720e)
//CANMBX1D .set 720Fh //; CAN 2 of 8 bytes of Mailbox 1
#define CANMBX1D (*(volatile unsigned int*) 0x720f)
//CANMSGID2L .set 7210h //; CAN Message ID for mailbox 2 (lower 16 bits)
#define CANMSGID2L (*(volatile unsigned int*) 0x7210)
//CANMSGID2H .set 7211h //; CAN Message ID for mailbox 2 (upper 16 bits)
#define CANMSGID2H (*(volatile unsigned int*) 0x7211)
//CANMSGCTRL2 .set 7212h //; CAN RTR and DLC
#define CANMSGCTRL2 (*(volatile unsigned int*) 0x7212)
//CANMBX2A .set 7214h //; CAN 2 of 8 bytes of Mailbox 2
#define CANMBX2A (*(volatile unsigned int*) 0x7214)
//CANMBX2B .set 7215h //; CAN 2 of 8 bytes of Mailbox 2
#define CANMBX2B (*(volatile unsigned int*) 0x7215)
//CANMBX2C .set 7216h //; CAN 2 of 8 bytes of Mailbox 2
#define CANMBX2C (*(volatile unsigned int*) 0x7216)
//CANMBX2D .set 7217h //; CAN 2 of 8 bytes of Mailbox 2
#define CANMBX2D (*(volatile unsigned int*) 0x7217)
//CANMSGID3L .set 7218h //; CAN Message ID for mailbox 3 (lower 16 bits)
#define CANMSGID3L (*(volatile unsigned int*) 0x7218)
//CANMSGID3H .set 7219h //; CAN Message ID for mailbox 3 (upper 16 bits)
#define CANMSGID3H (*(volatile unsigned int*) 0x7219)
//CANMSGCTRL3 .set 721Ah //; CAN RTR and DLC
#define CANMSGCTRL3 (*(volatile unsigned int*) 0x721a)
//CANMBX3A .set 721Ch //; CAN 2 of 8 bytes of Mailbox 3
#define CANMBX3A (*(volatile unsigned int*) 0x721c)
//CANMBX3B .set 721Dh //; CAN 2 of 8 bytes of Mailbox 3
#define CANMBX3B (*(volatile unsigned int*) 0x721d)
//CANMBX3C .set 721Eh //; CAN 2 of 8 bytes of Mailbox 3
#define CANMBX3C (*(volatile unsigned int*) 0x721e)
//CANMBX3D .set 721Fh //; CAN 2 of 8 bytes of Mailbox 3
#define CANMBX3D (*(volatile unsigned int*) 0x721f)
//CANMSGID4L .set 7220h //; CAN Message ID for mailbox 4 (lower 16 bits)
#define CANMSGID4L (*(volatile unsigned int*) 0x7220)
//CANMSGID4H .set 7221h //; CAN Message ID for mailbox 4 (upper 16 bits)
#define CANMSGID4H (*(volatile unsigned int*) 0x7221)
//CANMSGCTRL4 .set 7222h //; CAN RTR and DLC
#define CANMSGCTRL4 (*(volatile unsigned int*) 0x7222)
//CANMBX4A .set 7224h //; CAN 2 of 8 bytes of Mailbox 4
#define CANMBX4A (*(volatile unsigned int*) 0x7224)
//CANMBX4B .set 7225h //; CAN 2 of 8 bytes of Mailbox 4
#define CANMBX4B (*(volatile unsigned int*) 0x7225)
//CANMBX4C .set 7226h //; CAN 2 of 8 bytes of Mailbox 4
#define CANMBX4C (*(volatile unsigned int*) 0x7226)
//CANMBX4D .set 7227h //; CAN 2 of 8 bytes of Mailbox 4
#define CANMBX4D (*(volatile unsigned int*) 0x7227)
//CANMSGID5L .set 7228h //; CAN Message ID for mailbox 5 (lower 16 bits)
#define CANMSGID5L (*(volatile unsigned int*) 0x7228)
//CANMSGID5H .set 7229h //; CAN Message ID for mailbox 5 (upper 16 bits)
#define CANMSGID5H (*(volatile unsigned int*) 0x7229)
//CANMSGCTRL5 .set 722Ah //; CAN RTR and DLC
#define CANMSGCTRL5 (*(volatile unsigned int*) 0x722a)
//CANMBX5A .set 722Ch //; CAN 2 of 8 bytes of Mailbox 5
#define CANMBX5A (*(volatile unsigned int*) 0x722c)
//CANMBX5B .set 722Dh //; CAN 2 of 8 bytes of Mailbox 5
#define CANMBX5B (*(volatile unsigned int*) 0x722d)
//CANMBX5C .set 722Eh //; CAN 2 of 8 bytes of Mailbox 5
#define CANMBX5C (*(volatile unsigned int*) 0x722e)
//CANMBX5D .set 722Fh //; CAN 2 of 8 bytes of Mailbox 5
#define CANMBX5D (*(volatile unsigned int*) 0x722f)

//; Code security module (CSM) registers (Data memory)
//KEY3 .set 77F0h //; High word of the 64-bit KEY register
#define KEY3 (*(volatile unsigned int*) 0x77f0)
//KEY2 .set 77F1h //; Third word of the 64-bit KEY register
#define KEY2 (*(volatile unsigned int*) 0x77f1)
//KEY1 .set 77F2h //; Second word of the 64-bit KEY register
#define KEY1 (*(volatile unsigned int*) 0x77f2)
//KEY0 .set 77F3h //; Low word of the 64-bit KEY register
#define KEY0 (*(volatile unsigned int*) 0x77f3)

//; Code security module (CSM) registers (Program memory)
//PWL3 .set 0040h //; High word of the 64–bit password
#define PWL3 (*(volatile unsigned int*) 0x0040)
//PWL2 .set 0041h //; Third word of the 64–bit password
#define PWL2 (*(volatile unsigned int*) 0x0041)
//PWL1 .set 0042h //; Second word of the 64–bit password
#define PWL1 (*(volatile unsigned int*) 0x0042)
//PWL0 .set 0043h //; Low word of the 64–bit password
#define PWL0 (*(volatile unsigned int*) 0x0043)
//;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

//; I/O space mapped registers
//;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
//WSGR .set 0FFFFh //; Wait-State Generator Control register
ioport    volatile unsigned int portffff; 
#define   WSGR    portffff 

//#define WSGR (*(volatile unsigned int*) 0xffff)
//FCMR .set 0FF0Fh //; Flash control mode register
ioport  volatile unsigned int portff0f;
#define   FCMR    portff0f
 
//#define FCMR (*(volatile unsigned int*) 0xff0f)
//;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
//; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
//;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
/*
BIT15 .set 0000h //; Bit Code for 15
BIT14 .set 0001h //; Bit Code for 14
BIT13 .set 0002h //; Bit Code for 13
BIT12 .set 0003h //; Bit Code for 12
BIT11 .set 0004h //; Bit Code for 11
BIT10 .set 0005h //; Bit Code for 10

BIT9 .set 0006h //; Bit Code for 9
BIT8 .set 0007h //; Bit Code for 8
BIT7 .set 0008h //; Bit Code for 7
BIT6 .set 0009h //; Bit Code for 6
BIT5 .set 000Ah //; Bit Code for 5
BIT4 .set 000Bh //; Bit Code for 4
BIT3 .set 000Ch //; Bit Code for 3
BIT2 .set 000Dh //; Bit Code for 2
BIT1 .set 000Eh //; Bit Code for 1
BIT0 .set 000Fh //; Bit Code for 0 */