f2407_c.h

一个简单明了的电压空间矢量pwm程序

//;************************************************************************
//; File name: 240x.h
//;
//; Description: 240x register definitions, Bit codes for BIT instruction
//;************************************************************************
//; 240x CPU core registers
//modifed WSGR & MCFR 2003.3.3
//IMR .set 0004h //; Interrupt Mask Register
#define IMR (*(volatile unsigned int*) 0x0004)
// IFR .set 0006h //; Interrupt Flag Register
#define IFR (*(volatile unsigned int*) 0x0006)

//; System configuration and interrupt registers
//SCSR1 .set 7018h //; System Control & Status register. 1
#define SCSR1 (*(volatile unsigned int*) 0x7018)
//SCSR2 .set 7019h //; System Control & Status register. 2
#define SCSR2 (*(volatile unsigned int*) 0x7019)
//DINR .set 701Ch //; Device Identification Number register.
#define DINR (*(volatile unsigned int*) 0x701C)
//PIVR .set 701Eh //; Peripheral Interrupt Vector register.
#define PIVR (*(volatile unsigned int*) 0x701E)
//PIRQR0 .set 7010h //; Peripheral Interrupt Request register 0
#define PIRQR0 (*(volatile unsigned int*) 0x7010)
//PIRQR1 .set 7011h //; Peripheral Interrupt Request register 1
#define PIRQR1 (*(volatile unsigned int*) 0x7011)
//PIRQR2 .set 7012h //; Peripheral Interrupt Request register 2
#define PIRQR2 (*(volatile unsigned int*) 0x7012)
//PIACKR0 .set 7014h //; Peripheral Interrupt Acknowledge register 0
#define PIACKR0 (*(volatile unsigned int*) 0x7014)
//PIACKR1 .set 7015h //; Peripheral Interrupt Acknowledge register 1
#define PIACKR1 (*(volatile unsigned int*) 0x7015)
//PIACKR2 .set 7016h //; Peripheral Interrupt Acknowledge register 2
#define PIACKR2 (*(volatile unsigned int*) 0x7016)

//; External interrupt configuration registers
//XINT1CR .set 7070h //; External interrupt 1 control register
#define XINT1CR (*(volatile unsigned int*) 0x7070)
//XINT2CR .set 7071h //; External interrupt 2 control register
#define XINT2CR (*(volatile unsigned int*) 0x7071)

//; Digital I/O registers
//MCRA .set 7090h //; I/O Mux Control Register A
#define MCRA (*(volatile unsigned int*) 0x7090)
//MCRB .set 7092h //; I/O Mux Control Register B
#define MCRB (*(volatile unsigned int*) 0x7092)
//MCRC .set 7094h //; I/O Mux Control Register C
#define MCRC (*(volatile unsigned int*) 0x7094)
//PADATDIR .set 7098h //; I/O port A Data & Direction register
#define PADATDIR (*(volatile unsigned int*) 0x7098)
//PBDATDIR .set 709Ah //; I/O port B Data & Direction register
#define PBDATDIR (*(volatile unsigned int*) 0x709A)
//PCDATDIR .set 709Ch //; I/O port C Data & Direction register
#define PCDATDIR (*(volatile unsigned int*) 0x709C)
//PDDATDIR .set 709Eh //; I/O port D Data & Direction register
#define PDDATDIR (*(volatile unsigned int*) 0x709E)
//PEDATDIR .set 7095h //; I/O port E Data & Direction register
#define PEDATDIR (*(volatile unsigned int*) 0x7095)
//PFDATDIR .set 7096h //; I/O port F Data & Direction register
#define PFDATDIR (*(volatile unsigned int*) 0x7096)

//; Watchdog (WD) registers
//WDCNTR .set 7023h //; WD Counter register
#define WDCNTR (*(volatile unsigned int*) 0x7023)
//WDKEY .set 7025h //; WD Key register
#define WDKEY (*(volatile unsigned int*) 0x7025)
//WDCR .set 7029h //; WD Control register
#define WDCR (*(volatile unsigned int*) 0x7029)

//; ADC registers
//ADCTRL1 .set 70A0h //; ADC Control register 1
#define ADCTRL1 (*(volatile unsigned int*) 0x70A0)
//ADCTRL2 .set 70A1h //; ADC Control register 2
#define ADCTRL2 (*(volatile unsigned int*) 0x70A1)
//MAXCONV .set 70A2h //; Maximum conversion channels register
#define MAXCONV (*(volatile unsigned int*) 0x70A2)
//CHSELSEQ1 .set 70A3h //; Channel select Sequencing control register 1
#define CHSELSEQ1 (*(volatile unsigned int*) 0x70A3)
//CHSELSEQ2 .set 70A4h //; Channel select Sequencing control register 2
#define CHSELSEQ2 (*(volatile unsigned int*) 0x70A4)
//CHSELSEQ3 .set 70A5h //; Channel select Sequencing control register 3
#define CHSELSEQ3 (*(volatile unsigned int*) 0x70A5)
//CHSELSEQ4 .set 70A6h //; Channel select Sequencing control register 4
#define CHSELSEQ4 (*(volatile unsigned int*) 0x70A6)
//AUTO_SEQ_SR .set 70A7h //; Auto–sequence status register
#define AUTO_SEQ_SR (*(volatile unsigned int*) 0x70A7)
//RESULT0 .set 70A8h //; Conversion result register 0
#define RESULT0 (*(volatile unsigned int*) 0x70A8)
//RESULT1 .set 70A9h //; Conversion result register 1
#define RESULT1 (*(volatile unsigned int*) 0x70A9)
//RESULT2 .set 70Aah //; Conversion result register 2
#define RESULT2 (*(volatile unsigned int*) 0x70Aa)
//RESULT3 .set 70Abh //; Conversion result register 3
#define RESULT3 (*(volatile unsigned int*) 0x70Ab)
//RESULT4 .set 70Ach //; Conversion result register 4
#define RESULT4 (*(volatile unsigned int*) 0x70Ac)
//RESULT5 .set 70Adh //; Conversion result register 5
#define RESULT5 (*(volatile unsigned int*) 0x70Ad)
//RESULT6 .set 70Aeh //; Conversion result register 6
#define RESULT6 (*(volatile unsigned int*) 0x70Ae)
//ESULT7 .set 70Afh //; Conversion result register 7
#define RESULT7 (*(volatile unsigned int*) 0x70Af)
//RESULT8 .set 70B0h //; Conversion result register 8
#define RESULT8 (*(volatile unsigned int*) 0x70B0)
//RESULT9 .set 70B1h //; Conversion result register 9
#define RESULT9 (*(volatile unsigned int*) 0x70B1)
//RESULT10 .set 70B2h //; Conversion result register 10
#define RESULT10 (*(volatile unsigned int*) 0x70B2)
//RESULT11 .set 70B3h //; Conversion result register 11
#define RESULT11 (*(volatile unsigned int*) 0x70B3)
//RESULT12 .set 70B4h //; Conversion result register 12
#define RESULT12 (*(volatile unsigned int*) 0x70B4)
//RESULT13 .set 70B5h //; Conversion result register 13
#define RESULT13 (*(volatile unsigned int*) 0x70B5)
//RESULT14 .set 70B6h //; Conversion result register 14
#define RESULT14 (*(volatile unsigned int*) 0x70B6)
//RESULT15 .set 70B7h //; Conversion result register 15
#define RESULT15 (*(volatile unsigned int*) 0x70B7)
//CALIBRATION .set 70B8h //; Calibration result, used to correct
#define CALIBRATION (*(volatile unsigned int*) 0x70B8)

//; subsequent conversions
//; SPI registers
//SPICCR .set 7040h //; SPI Config Control register
#define SPICCR (*(volatile unsigned int*) 0x7040)
//SPICTL .set 7041h //; SPI Operation Control register
#define SPICTL (*(volatile unsigned int*) 0x7041)
//SPISTS .set 7042h //; SPI Status register
#define SPISTS (*(volatile unsigned int*) 0x7042)
//SPIBRR .set 7044h //; SPI Baud rate control register
#define SPIBRR (*(volatile unsigned int*) 0x7044)
//SPIRXEMU .set 7046h //; SPI Emulation buffer register
#define SPIRXEMU (*(volatile unsigned int*) 0x7046)
//SPIRXBUF .set 7047h //; SPI Serial receive buffer register
#define SPIRXBUF (*(volatile unsigned int*) 0x7047)
//SPITXBUF .set 7048h //; SPI Serial transmit buffer register
#define SPITXBUF (*(volatile unsigned int*) 0x7048)
//SPIDAT .set 7049h //; SPI Serial data register
#define SPIDAT (*(volatile unsigned int*) 0x7049)
//SPIPRI .set 704Fh //; SPI Priority control register
#define SPIPRI (*(volatile unsigned int*) 0x704F)

//; SCI registers
//SCICCR .set 7050h //; SCI Communication control register
#define SCICCR (*(volatile unsigned int*) 0x7050)
//SCICTL1 .set 7051h //; SCI Control register 1
#define SCICTL1 (*(volatile unsigned int*) 0x7051)
//SCIHBAUD .set 7052h //; SCI Baud Rate MS byte register
#define SCIHBAUD (*(volatile unsigned int*) 0x7052)
//SCILBAUD .set 7053h //; SCI Baud Rate LS byte register
#define SCILBAUD (*(volatile unsigned int*) 0x7053)
//SCICTL2 .set 7054h //; SCI Control register 2
#define SCICTL2 (*(volatile unsigned int*) 0x7054)
//SCIRXST .set 7055h //; SCI Receiver Status register
#define SCIRXST (*(volatile unsigned int*) 0x7055)
//SCIRXEMU .set 7056h //; SCI Emulation Data Buffer register
#define SCIRXEMU (*(volatile unsigned int*) 0x7056)
//SCIRXBUF .set 7057h //; SCI Receiver Data buffer register
#define SCIRXBUF (*(volatile unsigned int*) 0x7057)
//SCITXBUF .set 7059h //; SCI Transmit Data buffer register
#define SCITXBUF (*(volatile unsigned int*) 0x7059)
//SCIPRI .set 705Fh //; SCI Priority control register
#define SCIPRI (*(volatile unsigned int*) 0x705F)

//; Event Manager A (EVA) registers
//GPTCONA .set 7400h //; GP Timer control register A
#define GPTCONA (*(volatile unsigned int*) 0x7400)
//T1CNT .set 7401h //; GP Timer 1 counter register
#define T1CNT (*(volatile unsigned int*) 0x7401)
//T1CMPR .set 7402h //; GP Timer 1 compare register
#define T1CMPR (*(volatile unsigned int*) 0x7402)
//T1PR .set 7403h //; GP Timer 1 period register
#define T1PR (*(volatile unsigned int*) 0x7403)
//T1CON .set 7404h //; GP Timer 1 control register
#define T1CON (*(volatile unsigned int*) 0x7404)
//T2CNT .set 7405h //; GP Timer 2 counter register
#define T2CNT (*(volatile unsigned int*) 0x7405)
//T2CMPR .set 7406h //; GP Timer 2 compare register
#define T2CMPR (*(volatile unsigned int*) 0x7406)
//T2PR .set 7407h //; GP Timer 2 period register
#define T2PR (*(volatile unsigned int*) 0x7407)
//T2CON .set 7408h //; GP Timer 2 control register
#define T2CON (*(volatile unsigned int*) 0x7408)
//COMCONA .set 7411h //; Compare control register A
#define COMCONA (*(volatile unsigned int*) 0x7411)
//ACTRA .set 7413h //; Full compare Action control register A
#define ACTRA (*(volatile unsigned int*) 0x7413)
//DBTCONA .set 7415h //; Dead-band timer control register A
#define DBTCONA (*(volatile unsigned int*) 0x7415)
//CMPR1 .set 7417h //; Full compare unit compare register1
#define CMPR1 (*(volatile unsigned int*) 0x7417)
//CMPR2 .set 7418h //; Full compare unit compare register2
#define CMPR2 (*(volatile unsigned int*) 0x7418)
//CMPR3 .set 7419h //; Full compare unit compare register3
#define CMPR3 (*(volatile unsigned int*) 0x7419)
//CAPCONA .set 7420h //; Capture control register A
#define CAPCONA (*(volatile unsigned int*) 0x7420)
//CAPFIFOA .set 7422h //; Capture FIFO status register A
#define CAPFIFOA (*(volatile unsigned int*) 0x7422)
//CAP1FIFO .set 7423h //; Capture Channel 1 FIFO Top
#define CAP1FIFO (*(volatile unsigned int*) 0x7423)
//CAP2FIFO .set 7424h //; Capture Channel 2 FIFO Top
#define CAP2FIFO (*(volatile unsigned int*) 0x7424)
//CAP3FIFO .set 7425h //; Capture Channel 3 FIFO Top
#define CAP3FIFO (*(volatile unsigned int*) 0x7425)
//CAP1FBOT .set 7427h //; Bottom reg. of capture FIFO stack 1
#define CAP1FBOT (*(volatile unsigned int*) 0x7427)
//CAP2FBOT .set 7428h //; Bottom reg. of capture FIFO stack 2
#define CAP2FBOT (*(volatile unsigned int*) 0x7428)
//CAP3FBOT .set 7429h //; Bottom reg. of capture FIFO stack 3
#define CAP3FBOT (*(volatile unsigned int*) 0x7429)
//EVAIMRA .set 742Ch //; Group A Interrupt Mask Register
#define EVAIMRA (*(volatile unsigned int*) 0x742C)
//EVAIMRB .set 742Dh //; Group B Interrupt Mask Register
#define EVAIMRB (*(volatile unsigned int*) 0x742D)
//EVAIMRC .set 742Eh //; Group C Interrupt Mask Register
#define EVAIMRC (*(volatile unsigned int*) 0x742E)
//EVAIFRA .set 742Fh //; Group A Interrupt Flag Register
#define EVAIFRA (*(volatile unsigned int*) 0x742F)
//EVAIFRB .set 7430h //; Group B Interrupt Flag Register
#define EVAIFRB (*(volatile unsigned int*) 0x7430)
//EVAIFRC .set 7431h //; Group C Interrupt Flag Register
#define EVAIFRC (*(volatile unsigned int*) 0x7431)

//; Event Manager B (EVB) registers
//GPTCONB .set 7500h //; GP Timer control register B
#define GPTCONB (*(volatile unsigned int*) 0x7500)