lv2410xreg.h

LV24000的单片机DEMO程序

/* ************************************************************************************************
 *
 *  Filename:	LV2410xReg.h (ImRadioIc3Reg.h)
 *  Project:    LV24-EVK
 *  Authors:	Hung van Le
 *  Purpose:    Extra Register/Bit definitions for LV24100/LV24101/LV24102
 *  Comments:   The LV2410x is a super set of LV2400x. The file LV2400xReg.h must also be included
 * ************************************************************************************************
 *  History:
 *  Version	Date		Author		Reason
 *    1.00	14-Oct-2004	HLE			- Initial version
 *
 * ************************************************************************************************
 * THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED 
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS 
 * FOR A PARTICULAR PURPOSE.
 *
 * Copyright (c) 2004. Semiconductor Ideas to the Market (ItoM) B.V. All rights reserved.
 * ************************************************************************************************ */

#if !defined(IM_RADIO_IC3_H__INCLUDED_)
#define IM_RADIO_IC3_H__INCLUDED_

#include "Lv2400xReg.h"		// For FM registers

//////////////////////////////////////////////////////////////////////
// New registers (LV2410x-ES1 only)
//////////////////////////////////////////////////////////////////////
#define IR03_AM_ACAPLOW_REG		0x0302	// Block 3-Reg02 (W): AM antenna capacitor (low byte)
#define IR03_AM_FE_REG			0x0303	// Block 3-Reg03 (W): AM front end control & AA cap high
#define IR03_AM_CTRL_REG		0x0304	// Block 3-Reg04 (W): AM control register 

//////////////////////////////////////////////////////////////////////
// Extra bits for LV2410x (differences from LV2400x)
//////////////////////////////////////////////////////////////////////
// ----- IR01_MSRC_SEL_REG extra bits (0x0102)
#define	IR3_MSRCS_MSS_AM	((BYTE)0x1<<3)	    // Bit 3: Enable AM antenna measurement when 1
	// Measured source mask for IR03
#define IR3_MSRCS_MSS_MASK	(IR1_MSRCS_MSS_FM|IR1_MSRCS_MSS_SD|IR1_MSRCS_MSS_IF|IR3_MSRCS_MSS_AM)

// ----- IR01_RADIO_CTRL1_REG extra bits (0x0202)
#define	IR3_RCTL1_AM_CD2		((BYTE)0x1<<4)	// Bit 4: RF clock divider for AM bit 2
#define	IR3_RCTL1_AM_CD1		((BYTE)0x1<<1)	// Bit 1: RF clock divider for AM bit 1
#define	IR3_RCTL1_AM_CD0		((BYTE)0x1<<0)	// Bit 0: RF clock divider for AM bit 0

	// Mask and register setting for divider factor
#define IR3_RCTL1_AM_CLKDIV_MSK	((BYTE)(IR3_RCTL1_AM_CD0|IR3_RCTL1_AM_CD1|IR3_RCTL1_AM_CD2))
#define IR3_AMDIV_48	((BYTE)(0))													// 0
#define IR3_AMDIV_64 	((BYTE)(IR3_RCTL1_AM_CD0))									// 1
#define IR3_AMDIV_80 	((BYTE)(IR3_RCTL1_AM_CD1))									// 2
#define IR3_AMDIV_96 	((BYTE)(IR3_RCTL1_AM_CD1|IR3_RCTL1_AM_CD0))					// 3
#define IR3_AMDIV_128	((BYTE)(IR3_RCTL1_AM_CD2))									// 4
#define IR3_AMDIV_160	((BYTE)(IR3_RCTL1_AM_CD2|IR3_RCTL1_AM_CD0))					// 5
#define IR3_AMDIV_192	((BYTE)(IR3_RCTL1_AM_CD2|IR3_RCTL1_AM_CD1))					// 6
#define IR3_AMDIV_OFF	((BYTE)(IR3_RCTL1_AM_CD2|IR3_RCTL1_AM_CD1|IR3_RCTL1_AM_CD0))// 7

// ----- IR01_RADIO_CTRL3_REG extra bits (0x0207)
#define	IR3_RCTL3_SE_AM			((BYTE)0x1<<2)	// Bit 2: Source enable: AM (is reserved for IMR01)
	// Radio band mask
#define IR3_RCTL3_AMFM_MASK     (IR1_RCTL3_SE_FM|IR3_RCTL3_SE_AM)
#define IR3_RCTL3_NO_AMFM       0                // Turn off AM/FM

//////////////////////////////////////////////////////////////////////
// Register layout - Block 3
//////////////////////////////////////////////////////////////////////
// ----- IR03_AM_ACAPLOW_REG (0x0302) layout
#define IR3_AACAP_LOW_MASK		((BYTE)0xFF)	// Bit [7:0]: AM antenna capacitor bit [7:0]

// ----- IR03_AM_FE_REG (0x0303) layout
#define	IR3_AFE_BIT7			((BYTE)0x1<<7)	// Bit 7: NA
#define	IR3_AFE_BIT6			((BYTE)0x1<<6)	// Bit 6: NA
#define	IR3_AFE_BIT5			((BYTE)0x1<<5)	// Bit 5: NA
#define	IR3_AFE_BIT4			((BYTE)0x1<<4)	// Bit 4: NA
#define	IR3_AFE_BIT3			((BYTE)0x1<<3)	// Bit 3: NA
#define	IR3_AFE_AGCSP			((BYTE)0x1<<2)	// Bit 2: Front end AGC speed
#define	IR3_AFE_AACAP9			((BYTE)0x1<<1)	// Bit 1: AM antenna capacitor bit 9
#define	IR3_AFE_AACAP8			((BYTE)0x1<<0)	// Bit 0: AM antenna capacitor bit 8
	// Some extra def. for AM ACAP
#define IR3_AACAP_HIGH_MASK		(IR3_AFE_AACAP9|IR3_AFE_AACAP8)	// High AM ACAP mask
#define IR3_AACAP_MASK			((BYTE)0x3FF)	// AM antenna capacitor is 10 bits width

// ----- IR03_AM_CTRL_REG (0x0304) layout
#define	IR3_AMCTL_AGC4_2		((BYTE)0x1<<7)	// Bit 7: AGC4 level bit 2
#define	IR3_AMCTL_AGC4_1		((BYTE)0x1<<6)	// Bit 6: AGC4 level bit 1
#define	IR3_AMCTL_AGC4_0		((BYTE)0x1<<5)	// Bit 5: AGC4 level bit 0
#define	IR3_AMCTL_FE_EN			((BYTE)0x1<<4)	// Bit 4: Enable AM front end when 1
#define	IR3_AMCTL_AM_CAL		((BYTE)0x1<<3)	// Bit 3: Enable AM antenna calibration when 1
#define	IR3_AMCTL_EGAIN_MX		((BYTE)0x1<<2)	// Bit 2: Extra gain mixer (1=on)
#define	IR3_AMCTL_AGC3_1		((BYTE)0x1<<1)	// Bit 1: AGC3 level bit 1
#define	IR3_AMCTL_AGC3_0		((BYTE)0x1<<0)	// Bit 0: AGC3 level bit 0

//////////////////////////////////////////////////////////////////////
#endif // !define IM_RADIO_IC3_H__INCLUDED_