x86emit.h

一个任天堂掌上游戏机NDS的源代码

#ifndef __X86_H_
#define __X86_H_

#include <stdio.h>
#include "datadefs.h"
#include "codeblock.h"

//---Opcode defines--------------------------------------------------------
//---Prefixes

#define PREFIX_OP      0x66
#define PREFIX_ADDR    0x67

#define PREFIX_ES      0x26
#define PREFIX_CS      0x2E
#define PREFIX_SS      0x36
#define PREFIX_DS      0x3E
#define PREFIX_FS      0x64
#define PREFIX_GS      0x65

#define PREFIX_LOCK    0xF0
#define PREFIX_REPNE   0xF2
#define PREFIX_REP     0xF3

//---Implied opcodes
#define XOP_AAA        0x37
#define XOP_AAD        0x0AD5
#define XOP_AAM        0x0AD4
#define XOP_AAS        0x3F
#define XOP_CDQ        0x99
#define XOP_CLC        0xF8
#define XOP_CLD        0xFC
#define XOP_CLI        0xFA
#define XOP_CMC        0xF5
#define XOP_CMPSB      0xF6
#define XOP_CMPSD      0xF7
#define XOP_CWDE       0x98
#define XOP_DAA        0x27
#define XOP_DAS        0x2F
#define XOP_HLT        0xF4
#define XOP_IN_reg8    0xEC
#define XOP_IN_reg32   0xED
#define XOP_INSB       0x6C
#define XOP_INSD       0x6D
#define XOP_INT3       0xCC
#define XOP_INTO       0xDE
#define XOP_IRET       0xCF
#define XOP_LAHF       0x9F
#define XOP_LEAVE      0xC9
#define XOP_LODSB      0xAC
#define XOP_LODSD      0xAD
#define XOP_MOVSB      0xA4
#define XOP_MOVSD      0xA5
#define XOP_NOP        0x90
#define XOP_OUT_reg8   0xEE
#define XOP_OUT_reg32  0xEF
#define XOP_OUTSB      0x6E
#define XOP_OUTSD      0x6F
#define XOP_POPAD      0x61
#define XOP_POPFD      0x9D
#define XOP_PUSHAD     0x60
#define XOP_PUSHFD     0x9C
#define XOP_RET        0xC3
#define XOP_RETF       0xCB
#define XOP_SAHF       0x9E
#define XOP_SCASB      0xAE
#define XOP_SCASD      0xAF
#define XOP_STC        0xF9
#define XOP_STD        0xFD
#define XOP_STI        0xFB
#define XOP_STOSB      0xAA
#define XOP_STOSD      0xAB
#define XOP_XLAT       0xD7
    
//---Using the ModRM encodings
#define XMOP_ADD 0
#define XMOP_OR  1
#define XMOP_ADC 2
#define XMOP_SBB 3
#define XMOP_AND 4
#define XMOP_SUB 5
#define XMOP_XOR 6
#define XMOP_CMP 7

#define XMOP_ROL 0
#define XMOP_ROR 1
#define XMOP_RCL 2
#define XMOP_RCR 3
#define XMOP_SHL 4
#define XMOP_SHR 5
#define XMOP_SAR 7

//---Registers-------------------------------------------------------------
enum X86Reg {
    al=0, cl, dl, bl, ah, ch, dh, bh,
    ax, cx, dx, bx, sp, bp, si, di,
    eax, ecx, edx, ebx, esp, ebp, esi, edi,
    es, cs, ss, ds, fs, gs
};

//---Condition encodings---------------------------------------------------
#define CC_O            0x00                    // overflow (OF=1)
#define CC_NO           0x01                    // not overflow (OF=0)
#define CC_B            0x02                    // below (CF=1)
#define CC_NAE          CC_B                    // 
#define CC_C            CC_B
#define CC_NB           0x03                    // above or equal (CF=0)
#define CC_NC           0x03                    //
#define CC_AE           CC_NB                   //
#define CC_E            0x04                    // zero (ZF=1)
#define CC_Z            CC_E                    //
#define CC_NE           0x05                    // not zero (ZF=0)
#define CC_NZ           CC_NE                   //
#define CC_BE           0x06                    // below or equal (CF=1 or ZF=1)
#define CC_NA           CC_BE                   //
#define CC_NBE          0x07                    // above (CF=0 and ZF=0)
#define CC_A            CC_NBE                  //
#define CC_S            0x08                    // sign (SF=1)
#define CC_NS           0x09                    // not sign (SF=0)
#define CC_P            0x0A                    // parity (PF=1)
#define CC_PE           CC_P                    //
#define CC_NP           0x0B                    // not parity (PF=0)
#define CC_PO           CC_NP                   //
#define CC_L            0x0C                    // less (SF<>OF)
#define CC_NGE          CC_L                    //
#define CC_NL           0x0D                    // not less (SF=OF)
#define CC_GE           CC_NL                   //
#define CC_LE           0x0E                    // less or equal (ZF=1 or SF<>OF)
#define CC_NG           CC_LE                   //
#define CC_NLE          0x0F                    // greater (ZF=0 and SF=OF)
#define CC_G            CC_NLE                  //

//---Helper defines--------------------------------------------------------
#define MOD(m)  ( ((m)&3) << 6 )
#define REG(r)  ( ((r)&7) << 3 )
#define RM(rm)  ( ((rm)&7) )

#define ModRM(mod,reg,rm)       ((u8)(MOD(mod) | REG(reg) | RM(rm)))

#define SIZECHECK(x) \
    switch(r) \
    { \
	case al: case cl: case dl: case bl: \
	case ah: case ch: case dh: case bh: \
            emit8((x)); \
	    break; \
	case eax: case ecx: case edx: case ebx: \
	case esp: case ebp: case esi: case edi: \
	    emit8((x)+1); \
	    break; \
    }

//---Instructions----------------------------------------------------------
#define sivoid static inline void

class x86 {

private:
    static CODEBLOCK *block;
    static u32 offset;

    //---ModRM-generic handlers
    sivoid mrm_reg_reg(X86Reg r, X86Reg s)
    {
        emit8(ModRM(3, s, r));
    }
    
    sivoid mrm_reg_mem(X86Reg r, X86Reg base)
    {
        emit8(ModRM(0, r, base));
    }
    
    sivoid mrm_reg_mem(X86Reg r, u32 disp)
    {
        emit8(ModRM(0, r, 5));
        emit32(disp);
    }

    sivoid mrm_reg_mem(X86Reg r, X86Reg base, u8 disp)
    {
        emit8(ModRM(1, r, base));
        emit8(disp);
    }
    
    sivoid mrm_reg_mem(X86Reg r, X86Reg base, u32 disp)
    {
        emit8(ModRM(2, r, base));
        emit32(disp);
    }
    
    sivoid mrm_reg_mem(X86Reg r, X86Reg base, X86Reg idx, int scale)
    {
        emit8(ModRM(0, r, 4));
        switch(scale)
        {
            case 1: emit8(ModRM(0, idx, base)); break;
            case 2: emit8(ModRM(1, idx, base)); break;
            case 4: emit8(ModRM(2, idx, base)); break;
            case 8: emit8(ModRM(3, idx, base)); break;
        }
    }
    
    sivoid mrm_reg_mem(X86Reg r, X86Reg base, X86Reg idx, int scale, u8 disp)
    {
        emit8(ModRM(1, r, 4));
        switch(scale)
        {
            case 1: emit8(ModRM(0, idx, base)); break;
            case 2: emit8(ModRM(1, idx, base)); break;
            case 4: emit8(ModRM(2, idx, base)); break;
            case 8: emit8(ModRM(3, idx, base)); break;
        }
        emit8(disp);
    }
    
    sivoid mrm_reg_mem(X86Reg r, X86Reg base, X86Reg idx, int scale, u32 disp)
    {
        emit8(ModRM(2, r, 4));
        switch(scale)
        {
            case 1: emit8(ModRM(0, idx, base)); break;
            case 2: emit8(ModRM(1, idx, base)); break;
            case 4: emit8(ModRM(2, idx, base)); break;
            case 8: emit8(ModRM(3, idx, base)); break;
        }
        emit32(disp);
    }
    
public:
    static void setblock(CODEBLOCK* blk)
    {
        block = blk;
	offset = 0;
	blk->target_size = 0;
    }
    
    sivoid emit8(u8 v) { block->target_addr[offset++]=v; (block->target_size)++; /*printf("EMIT %02X\n",v);*/ }
    sivoid emit16(u16 v) { emit8(v&255); emit8(v>>8); }
    sivoid emit32(u32 v) { emit8(v&255); emit8((v>>8)&255); emit8((v>>16)&255); emit8(v>>24); }

    //---Implied addressing
    sivoid imp(u16 op)
    {
	if(op&0xFF00) emit16(op);
	else emit8(op);
    }

    //---Dataproc-specific ModRM addressing
    sivoid dp_reg_reg(int op, X86Reg r, X86Reg s)
    {
	SIZECHECK(op*8); mrm_reg_reg(r, s);
    }
    
    sivoid dp_mem_reg(int op, X86Reg base, X86Reg r)
    {
        SIZECHECK(op*8); mrm_reg_mem(r, base);
    }
    
    sivoid dp_mem_reg(int op, u32 disp, X86Reg r)
    {
        SIZECHECK(op*8); mrm_reg_mem(r, disp);
    }
    
    sivoid dp_mem_reg(int op, X86Reg base, u8 disp, X86Reg r)
    {
        SIZECHECK(op*8); mrm_reg_mem(r, base, disp);
    }
    
    sivoid dp_mem_reg(int op, X86Reg base, u32 disp, X86Reg r)
    {
        SIZECHECK(op*8); mrm_reg_mem(r, base, disp);
    }
    
    sivoid dp_mem_reg(int op, X86Reg base, X86Reg idx, int scale, X86Reg r)
    {
        SIZECHECK(op*8); mrm_reg_mem(r, base, idx, scale);
    }
    
    sivoid dp_mem_reg(int op, X86Reg base, X86Reg idx, int scale, u8 disp, X86Reg r)
    {
        SIZECHECK(op*8); mrm_reg_mem(r, base, idx, scale, disp);
    }
    
    sivoid dp_mem_reg(int op, X86Reg base, X86Reg idx, int scale, u32 disp, X86Reg r)
    {
        SIZECHECK(op*8); mrm_reg_mem(r, base, idx, scale, disp);
    }
    
    sivoid dp_reg_mem(int op, X86Reg r, X86Reg base)
    {
        SIZECHECK(op*8+2); mrm_reg_mem(r, base);
    }
    
    sivoid dp_reg_mem(int op, X86Reg r, u32 disp)
    {
        SIZECHECK(op*8+2); mrm_reg_mem(r, disp);
    }
    
    sivoid dp_reg_mem(int op, X86Reg r, X86Reg base, u8 disp)
    {
        SIZECHECK(op*8+2); mrm_reg_mem(r, base, disp);
    }
    
    sivoid dp_reg_mem(int op, X86Reg r, X86Reg base, u32 disp)
    {
        SIZECHECK(op*8+2); mrm_reg_mem(r, base, disp);
    }
    
    sivoid dp_reg_mem(int op, X86Reg r, X86Reg base, X86Reg idx, int scale)
    {
        SIZECHECK(op*8+2); mrm_reg_mem(r, base, idx, scale);
    }
    
    sivoid dp_reg_mem(int op, X86Reg r, X86Reg base, X86Reg idx, int scale, u8 disp)
    {
        SIZECHECK(op*8+2); mrm_reg_mem(r, base, idx, scale, disp);
    }
    
    sivoid dp_reg_mem(int op, X86Reg r, X86Reg base, X86Reg idx, int scale, u32 disp)
    {
        SIZECHECK(op*8+2); mrm_reg_mem(r, base, idx, scale, disp);
    }
    
    sivoid dp_reg_imm(int op, X86Reg r, u8 imm)
    {
	if(r==al) { emit8(op*8+4); emit8(imm); }
	else      { emit8(0x80); mrm_reg_reg(r, (X86Reg)op); emit8(imm); }
    }
    
    sivoid dp_reg_imm(int op, X86Reg r, u32 imm)
    {
	if(r==eax) { emit8(op*8+5); emit32(imm); }
	else       { emit8(0x81); mrm_reg_reg(r, (X86Reg)op); emit32(imm); }
    }
    
    sivoid dp_mem_imm(int op, X86Reg base, u8 imm)
    {
	emit8(0x80); mrm_reg_mem((X86Reg)op, base); emit8(imm);
    }

    sivoid dp_mem_imm(int op, X86Reg base, u32 imm)
    {
	emit8(0x81); mrm_reg_mem((X86Reg)op, base); emit32(imm);
    }
    
    sivoid dp_mem_imm(int op, u32 disp, u8 imm)
    {
        emit8(0x80); mrm_reg_mem((X86Reg)op, disp); emit8(imm);
    }
    
    sivoid dp_mem_imm(int op, u32 disp, u32 imm)
    {
        emit8(0x81); mrm_reg_mem((X86Reg)op, disp); emit32(imm);
    }
    
    sivoid dp_mem_imm(int op, X86Reg base, u8 disp, u8 imm)
    {
	emit8(0x80); mrm_reg_mem((X86Reg)op, base, disp); emit8(imm);
    }
    
    sivoid dp_mem_imm(int op, X86Reg base, u32 disp, u8 imm)
    {
	emit8(0x80); mrm_reg_mem((X86Reg)op, base, disp); emit8(imm);
    }

    sivoid dp_mem_imm(int op, X86Reg base, u8 disp, u32 imm)
    {
	emit8(0x81); mrm_reg_mem((X86Reg)op, base, disp); emit32(imm);
    }

    sivoid dp_mem_imm(int op, X86Reg base, u32 disp, u32 imm)
    {
	emit8(0x81); mrm_reg_mem((X86Reg)op, base, disp); emit32(imm);
    }
    
    sivoid dp_mem_imm(int op, X86Reg base, X86Reg idx, int scale, u8 imm)
    {
        emit8(0x80); mrm_reg_mem((X86Reg)op, base, idx, scale); emit8(imm);
    }
   
    sivoid dp_mem_imm(int op, X86Reg base, X86Reg idx, int scale, u32 imm)
    {
        emit8(0x81); mrm_reg_mem((X86Reg)op, base, idx, scale); emit32(imm);
    }
   
    sivoid dp_mem_imm(int op, X86Reg base, X86Reg idx, int scale, u8 disp, u8 imm)
    {
        emit8(0x80); mrm_reg_mem((X86Reg)op, base, idx, scale, disp); emit8(imm);
    }
    
    sivoid dp_mem_imm(int op, X86Reg base, X86Reg idx, int scale, u8 disp, u32 imm)
    {
        emit8(0x81); mrm_reg_mem((X86Reg)op, base, idx, scale, disp); emit32(imm);
    }
    
    sivoid dp_mem_imm(int op, X86Reg base, X86Reg idx, int scale, u32 disp, u8 imm)
    {
        emit8(0x80); mrm_reg_mem((X86Reg)op, base, idx, scale, disp); emit8(imm);
    }
    
    sivoid dp_mem_imm(int op, X86Reg base, X86Reg idx, int scale, u32 disp, u32 imm)
    {
        emit8(0x81); mrm_reg_mem((X86Reg)op, base, idx, scale, disp); emit32(imm);
    }
    
    //---Shift-specific ModRM encodings
    sivoid shft_reg_imm(int op, X86Reg r, u8 imm)
    {
	if(imm>1) { SIZECHECK(0xC0); emit8(ModRM(3, op&7, r)); emit8(imm); }
	else      { SIZECHECK(0xD0); emit8(ModRM(3, op&7, r));             }
    }
    
    sivoid shft_memb_imm(int op, X86Reg base, u8 imm)
    {
	if(imm>1) { emit8(0xC0); mrm_reg_mem((X86Reg)op, base); emit8(imm); }
	else      { emit8(0xD0); mrm_reg_mem((X86Reg)op, base);             }
    }

    sivoid shft_memb_imm(int op, u32 disp, u8 imm)
    {
        if(imm>1) { emit8(0xC0); mrm_reg_mem((X86Reg)op, disp); emit8(imm); }
	else      { emit8(0xD0); mrm_reg_mem((X86Reg)op, disp);             }
    }
    
    sivoid shft_memb_imm(int op, X86Reg base, u8 disp, u8 imm)
    {
	if(imm>1) { emit8(0xC0); mrm_reg_mem((X86Reg)op, base, disp); emit8(imm); }
	else      { emit8(0xD0); mrm_reg_mem((X86Reg)op, base, disp);             }
    }
    
    sivoid shft_memb_imm(int op, X86Reg base, u32 disp, u8 imm)
    {
	if(imm>1) { emit8(0xC0); mrm_reg_mem((X86Reg)op, base, disp); emit8(imm); }
	else      { emit8(0xD0); mrm_reg_mem((X86Reg)op, base, disp);             }
    }

    sivoid shft_memb_imm(int op, X86Reg base, X86Reg idx, int scale, u8 imm)
    {
        if(imm>1) { emit8(0xC0); mrm_reg_mem((X86Reg)op, base, idx, scale); emit8(imm); }
	else      { emit8(0xD0); mrm_reg_mem((X86Reg)op, base, idx, scale);             }
    }
   
    sivoid shft_memb_imm(int op, X86Reg base, X86Reg idx, int scale, u8 disp, u8 imm)
    {
        if(imm>1) { emit8(0xC0); mrm_reg_mem((X86Reg)op, base, idx, scale, disp); emit8(imm); }
	else      { emit8(0xD0); mrm_reg_mem((X86Reg)op, base, idx, scale, disp);             }
    }
    
    sivoid shft_memb_imm(int op, X86Reg base, X86Reg idx, int scale, u32 disp, u8 imm)
    {
        if(imm>1) { emit8(0xC0); mrm_reg_mem((X86Reg)op, base, idx, scale, disp); emit8(imm); }
	else      { emit8(0xD0); mrm_reg_mem((X86Reg)op, base, idx, scale, disp);             }
    }
    
    sivoid shft_memd_imm(int op, X86Reg base, u8 imm)
    {
	if(imm>1) { emit8(0xC1); mrm_reg_mem((X86Reg)op, base); emit8(imm); }