arm-ls.cpp

一个任天堂掌上游戏机NDS的源代码

OPC opLDRBTofrpll(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrll); _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTofrplr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrlr); _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTofrpar(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrar); _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTofrprr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrrr); _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTprrmll(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrll); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}
OPC opLDRBTprrmlr(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrlr); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}
OPC opLDRBTprrmar(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrar); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}
OPC opLDRBTprrmrr(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrrr); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}
OPC opLDRBTprrpll(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrll); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}
OPC opLDRBTprrplr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrlr); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}
OPC opLDRBTprrpar(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrar); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}
OPC opLDRBTprrprr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrrr); LSwb; _RD=MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI);return 3;}

OPC opSTRBTptrmll(){ MMU->priv(MMU_PRIV_LO); LSptm(LSrll); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptrmlr(){ MMU->priv(MMU_PRIV_LO); LSptm(LSrlr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptrmar(){ MMU->priv(MMU_PRIV_LO); LSptm(LSrar); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptrmrr(){ MMU->priv(MMU_PRIV_LO); LSptm(LSrrr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptrpll(){ MMU->priv(MMU_PRIV_LO); LSptp(LSrll); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptrplr(){ MMU->priv(MMU_PRIV_LO); LSptp(LSrlr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptrpar(){ MMU->priv(MMU_PRIV_LO); LSptp(LSrar); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptrprr(){ MMU->priv(MMU_PRIV_LO); LSptp(LSrrr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrmll(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrll); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrmlr(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrlr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrmar(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrar); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrmrr(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrrr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrpll(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrll); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrplr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrlr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrpar(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrar); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofrprr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrrr); MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrmll(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrll); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrmlr(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrlr); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrmar(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrar); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrmrr(){ MMU->priv(MMU_PRIV_LO); LSofm(LSrrr); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrpll(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrll); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrplr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrlr); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrpar(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrar); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprrprr(){ MMU->priv(MMU_PRIV_LO); LSofp(LSrrr); LSwb; MMU->wrB(reg.tmp1,_RD&255); MMU->priv(MMU_PRIV_HI); return 2; }

// Load/store multiple is also in this file, since it's common between
// the cores.

//---Initial pointer setup-------------------------------------------------
// Note: Rn is written back differently dependent on direction

#define addrLMIA reg.tmp1 = (_RN&~3)
#define addrLMIB reg.tmp1 = (_RN&~3)+4
#define addrLMDA reg.tmp1 = (_RN&~3)-(ssum16(reg.curop&65535)*4)+4
#define addrLMDB reg.tmp1 = (_RN&~3)-(ssum16(reg.curop&65535)*4)

#define addrLMwi _RN += ssum16(reg.curop&65535)*4
#define addrLMwd _RN -= ssum16(reg.curop&65535)*4

//---Opcode defines (Simple loops, really)---------------------------------
// BUGBUG: User-mode LDM assumes linear storage of r0-r15 (safe assumption)

#define opLDM \
    for(int a=0;a<=14;a++) \
    { \
        if(reg.curop&(1<<a)) \
        { \
            reg.r[a]=MMU->rdW(reg.tmp1); \
            reg.tmp1+=4; \
        } \
    } \
    if(reg.curop&0x00008000) \
    { \
        reg.r[15]=MMU->rdW(reg.tmp1)&0xFFFFFFFC; \
        reg.tmp1+=4; \
    } \
    return 3

#define opSTM \
    for(int a=0;a<=15;a++) \
    { \
        if(reg.curop&(1<<a)) \
        { \
            MMU->wrW(reg.tmp1,reg.r[a]); \
            reg.tmp1+=4; \
        } \
    } \
    return 2

#define opLDMu \
    u32 curmode = reg.curmode; \
    u32 *userregs = &reg.r0; \
    modeSwitch(curmode, MODE_USR); \
    modeSwitch(MODE_USR, curmode); \
    for(int a=0;a<=14;a++) \
    { \
	if(reg.curop&(1<<a)) \
	{ \
	    userregs[a] = MMU->rdW(reg.tmp1); \
	    reg.tmp1+=4; \
	} \
    } \
    return 3

#define opSTMu \
    u32 curmode = reg.curmode; \
    u32 *userregs = &reg.r0; \
    modeSwitch(curmode, MODE_USR); \
    modeSwitch(MODE_USR, curmode); \
    for(int a=0;a<=15;a++) \
    { \
	if(reg.curop&(1<<a)) \
	{ \
	    MMU->wrW(reg.tmp1, userregs[a]); \
	    reg.tmp1+=4; \
	} \
    } \
    return 2

// Just as with the one-value load/store, once the opcodes are defined,
// it's a matter of plugging defines together.

OPC opLDMIA() { addrLMIA; opLDM; }
OPC opLDMIB() { addrLMIB; opLDM; }
OPC opLDMDA() { addrLMDA; opLDM; }
OPC opLDMDB() { addrLMDB; opLDM; }

OPC opLDMIAw() { addrLMIA; addrLMwi; opLDM; }
OPC opLDMIBw() { addrLMIB; addrLMwi; opLDM; }
OPC opLDMDAw() { addrLMDA; addrLMwd; opLDM; }
OPC opLDMDBw() { addrLMDB; addrLMwd; opLDM; }

OPC opSTMIA() { addrLMIA; opSTM; }
OPC opSTMIB() { addrLMIB; opSTM; }
OPC opSTMDA() { addrLMDA; opSTM; }
OPC opSTMDB() { addrLMDB; opSTM; }

OPC opSTMIAw() { addrLMIA; addrLMwi; opSTM; }
OPC opSTMIBw() { addrLMIB; addrLMwi; opSTM; }
OPC opSTMDAw() { addrLMDA; addrLMwd; opSTM; }
OPC opSTMDBw() { addrLMDB; addrLMwd; opSTM; }

OPC opLDMIAu() { addrLMIA; opLDMu; }
OPC opLDMIBu() { addrLMIB; opLDMu; }
OPC opLDMDAu() { addrLMDA; opLDMu; }
OPC opLDMDBu() { addrLMDB; opLDMu; }

OPC opLDMIAuw() { addrLMIA; addrLMwi; opLDMu; }
OPC opLDMIBuw() { addrLMIB; addrLMwi; opLDMu; }
OPC opLDMDAuw() { addrLMDA; addrLMwd; opLDMu; }
OPC opLDMDBuw() { addrLMDB; addrLMwd; opLDMu; }

OPC opSTMIAu() { addrLMIA; opSTMu; }
OPC opSTMIBu() { addrLMIB; opSTMu; }
OPC opSTMDAu() { addrLMDA; opSTMu; }
OPC opSTMDBu() { addrLMDB; opSTMu; }

OPC opSTMIAuw() { addrLMIA; addrLMwi; opSTMu; }
OPC opSTMIBuw() { addrLMIB; addrLMwi; opSTMu; }
OPC opSTMDAuw() { addrLMDA; addrLMwd; opSTMu; }
OPC opSTMDBuw() { addrLMDB; addrLMwd; opSTMu; }

/*** EOF: arm-ls.cpp *****************************************************/