arm-ls.cpp

一个任天堂掌上游戏机NDS的源代码

/**************************************************************************
* DSemu - The Next Generation                                             *
* Portable ARM cores: Common: Load/Store [arm-ls.cpp]                     *
* Copyright Imran Nazar, 2005; released under the BSD public licence.     *
**************************************************************************/

// __ARMHDR is set by the Makefile to be either arm7tdmi.h or arm9es.h
#include __ARMHDR

#include "armmasks.h"
#include "datadefs.h"
#include "plgmmu32.h"
#include "armhelp.h"

//---Addressing modes------------------------------------------------------
// Only a few defines need exist here, since the opcodes themselves
// combine them in many configurations. The combination method must be:
// Offset addressing: [ofm|ofp]([Si|Hi|Hr|Sr*]);
// Pre-indexed: [ofm|ofp]([Si|Hi|Hr|Sr*]); wb;
// Post-indexed: [ptm|ptp]([Si|Hi|Hr|Sr*]);

// NOTE: Halfword-style opcodes address their immediates in a different
//       way to the standard word/byte LS.

#define LSofm if(_OP_RM==15) opUNP(); reg.tmp1 = _RN + Rn15hack -
#define LSofp if(_OP_RM==15) opUNP(); reg.tmp1 = _RN + Rn15hack +

#define LSwb _RN = reg.tmp1

#define LSptm if(_OP_RM==15 || _OP_RN==15) opUNP(); reg.tmp1 = _RN + Rn15hack; _RN -=
#define LSptp if(_OP_RM==15 || _OP_RN==15) opUNP(); reg.tmp1 = _RN + Rn15hack; _RN +=

#define LSi (reg.curop&MSK_IMM12)

#define LHi ((reg.curop&MSK_RM)|((reg.curop&MSK_RS)>>4))
#define LHr _RM + Rm15hack

#define LSrll ((_RM+Rm15hack) << helpDPshfti)
#define LSrlr ((helpDPshfti) ? ((_RM+Rm15hack) >> (helpDPshfti)) : 0)
#define LSrar ((helpDPshfti) ? ((signed)(_RM+Rm15hack) >> (helpDPshfti)) : (((_RM+Rm15hack)>>31)?0xFFFFFFFF:0))
#define LSrrr ((helpDPshfti)?(_ROR(_RM+Rm15hack,helpDPshfti)):(((_RM+Rm15hack)>>1)|(reg.flags[FLAG_C]<<31)))

//---Simple and halfword-style addressing----------------------------------
								 
OPC opLDRptim(){ LSptm(LSi); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRptip(){ LSptp(LSi); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRofim(){ LSofm(LSi); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRofip(){ LSofp(LSi); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRprim(){ LSofm(LSi); LSwb; _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRprip(){ LSofp(LSi); LSwb; _RD=MMU->rdW(reg.tmp1); LSror; return 3; }

OPC opSTRptim(){ LSptm(LSi); MMU->wrW(reg.tmp1,_RD); return 2; }
OPC opSTRptip(){ LSptp(LSi); MMU->wrW(reg.tmp1,_RD); return 2; }
OPC opSTRofim(){ LSofm(LSi); MMU->wrW(reg.tmp1,_RD); return 2; }
OPC opSTRofip(){ LSofp(LSi); MMU->wrW(reg.tmp1,_RD); return 2; }
OPC opSTRprim(){ LSofm(LSi); LSwb; MMU->wrW(reg.tmp1,_RD); return 2; }
OPC opSTRprip(){ LSofp(LSi); LSwb; MMU->wrW(reg.tmp1,_RD); return 2; }

OPC opLDRBptim(){ LSptm(LSi); _RD=MMU->rdB(reg.tmp1); return 3; }
OPC opLDRBptip(){ LSptp(LSi); _RD=MMU->rdB(reg.tmp1); return 3; }
OPC opLDRBofim(){ LSofm(LSi); _RD=MMU->rdB(reg.tmp1); return 3; }
OPC opLDRBofip(){ LSofp(LSi); _RD=MMU->rdB(reg.tmp1); return 3; }
OPC opLDRBprim(){ LSofm(LSi); LSwb; _RD=MMU->rdB(reg.tmp1); return 3; }
OPC opLDRBprip(){ LSofp(LSi); LSwb; _RD=MMU->rdB(reg.tmp1); return 3; }

OPC opSTRBptim(){ LSptm(LSi); MMU->wrB(reg.tmp1,(_RD&255)); return 2; }
OPC opSTRBptip(){ LSptp(LSi); MMU->wrB(reg.tmp1,(_RD&255)); return 2; }
OPC opSTRBofim(){ LSofm(LSi); MMU->wrB(reg.tmp1,(_RD&255)); return 2; }
OPC opSTRBofip(){ LSofp(LSi); MMU->wrB(reg.tmp1,(_RD&255)); return 2; }
OPC opSTRBprim(){ LSofm(LSi); LSwb; MMU->wrB(reg.tmp1,(_RD&255)); return 2; }
OPC opSTRBprip(){ LSofp(LSi); LSwb; MMU->wrB(reg.tmp1,(_RD&255)); return 2; }

OPC opLDRHptim(){ LSptm(LHi); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHptip(){ LSptp(LHi); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHptrm(){ LSptm(LHr); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHptrp(){ LSptp(LHr); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHofim(){ LSofm(LHi); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHofip(){ LSofp(LHi); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHofrm(){ LSofm(LHr); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHofrp(){ LSofp(LHr); /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHprim(){ LSofm(LHi); LSwb; /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHprip(){ LSofp(LHi); LSwb; /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHprrm(){ LSofm(LHr); LSwb; /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }
OPC opLDRHprrp(){ LSofp(LHr); LSwb; /*if(reg.tmp1&1) opUNP();*/ _RD=MMU->rdH(reg.tmp1); return 3; }

OPC opSTRHptim(){ LSptm(LHi); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHptip(){ LSptp(LHi); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHptrm(){ LSptm(LHr); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHptrp(){ LSptp(LHr); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHofim(){ LSofm(LHi); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHofip(){ LSofp(LHi); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHofrm(){ LSofm(LHr); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHofrp(){ LSofp(LHr); /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2;}
OPC opSTRHprim(){ LSofm(LHi); LSwb; /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2; }
OPC opSTRHprip(){ LSofp(LHi); LSwb; /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2; }
OPC opSTRHprrm(){ LSofm(LHr); LSwb; /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2; }
OPC opSTRHprrp(){ LSofp(LHr); LSwb; /*if(reg.tmp1&1) opUNP();*/ MMU->wrH(reg.tmp1,_RD&65535); return 2; }

OPC opLDRTptim(){ MMU->priv(MMU_PRIV_LO); LSptm(LSi); _RD=MMU->rdW(reg.tmp1); LSror; MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRTptip(){ MMU->priv(MMU_PRIV_LO); LSptp(LSi); _RD=MMU->rdW(reg.tmp1); LSror; MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRTofim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); _RD=MMU->rdW(reg.tmp1); LSror; MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRTofip(){ MMU->priv(MMU_PRIV_LO); LSofp(LSi); _RD=MMU->rdW(reg.tmp1); LSror; MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRTprim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); LSwb; _RD=MMU->rdW(reg.tmp1); LSror; MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRTprip(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); LSwb; _RD=MMU->rdW(reg.tmp1); LSror; MMU->priv(MMU_PRIV_HI); return 3; }

OPC opSTRTptim(){ MMU->priv(MMU_PRIV_LO); LSptm(LSi); MMU->wrW(reg.tmp1,_RD); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRTptip(){ MMU->priv(MMU_PRIV_LO); LSptp(LSi); MMU->wrW(reg.tmp1,_RD); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRTofim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); MMU->wrW(reg.tmp1,_RD); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRTofip(){ MMU->priv(MMU_PRIV_LO); LSofp(LSi); MMU->wrW(reg.tmp1,_RD); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRTprim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); LSwb; MMU->wrW(reg.tmp1,_RD); MMU->priv(MMU_PRIV_HI); return 2;}
OPC opSTRTprip(){ MMU->priv(MMU_PRIV_LO); LSofp(LSi); LSwb; MMU->wrW(reg.tmp1,_RD); MMU->priv(MMU_PRIV_HI); return 2;}

OPC opLDRBTptim(){ MMU->priv(MMU_PRIV_LO); LSptm(LSi); _RD=(u32)MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTptip(){ MMU->priv(MMU_PRIV_LO); LSptp(LSi); _RD=(u32)MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTofim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); _RD=(u32)MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTofip(){ MMU->priv(MMU_PRIV_LO); LSofp(LSi); _RD=(u32)MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTprim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); LSwb; _RD=(u32)MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }
OPC opLDRBTprip(){ MMU->priv(MMU_PRIV_LO); LSofp(LSi); LSwb; _RD=(u32)MMU->rdB(reg.tmp1); MMU->priv(MMU_PRIV_HI); return 3; }

OPC opSTRBTptim(){ MMU->priv(MMU_PRIV_LO); LSptm(LSi); MMU->wrB(reg.tmp1,(_RD&255)); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTptip(){ MMU->priv(MMU_PRIV_LO); LSptp(LSi); MMU->wrB(reg.tmp1,(_RD&255)); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); MMU->wrB(reg.tmp1,(_RD&255)); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTofip(){ MMU->priv(MMU_PRIV_LO); LSofp(LSi); MMU->wrB(reg.tmp1,(_RD&255)); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprim(){ MMU->priv(MMU_PRIV_LO); LSofm(LSi); LSwb; MMU->wrB(reg.tmp1,(_RD&255)); MMU->priv(MMU_PRIV_HI); return 2; }
OPC opSTRBTprip(){ MMU->priv(MMU_PRIV_LO); LSofp(LSi); LSwb; MMU->wrB(reg.tmp1,(_RD&255)); MMU->priv(MMU_PRIV_HI); return 2; }

OPC opLDRSBptim(){ LSptm(LHi); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBptip(){ LSptp(LHi); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBptrm(){ LSptm(LHr); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBptrp(){ LSptp(LHr); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBofim(){ LSofm(LHi); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBofip(){ LSofp(LHi); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBofrm(){ LSofm(LHr); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBofrp(){ LSofp(LHr); reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBprim(){ LSofm(LHi); LSwb; reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBprip(){ LSofp(LHi); LSwb; reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBprrm(){ LSofm(LHr); LSwb; reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }
OPC opLDRSBprrp(){ LSofp(LHr); LSwb; reg.tmp2=MMU->rdB(reg.tmp1); _RD=(reg.tmp2&128)?(0xFFFFFF00|reg.tmp2):reg.tmp2; return 3; }

OPC opLDRSHptim(){ LSptm(LHi); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHptip(){ LSptp(LHi); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHptrm(){ LSptm(LHr); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHptrp(){ LSptp(LHr); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHofim(){ LSofm(LHi); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHofip(){ LSofp(LHi); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHofrm(){ LSofm(LHr); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHofrp(){ LSofp(LHr); reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHprim(){ LSofm(LHi); LSwb; reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHprip(){ LSofp(LHi); LSwb; reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHprrm(){ LSofm(LHr); LSwb; reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }
OPC opLDRSHprrp(){ LSofp(LHr); LSwb; reg.tmp2=MMU->rdH(reg.tmp1); _RD=(reg.tmp2&32768)?(0xFFFF0000|reg.tmp2):reg.tmp2; return 2; }

//---Shifted addressing (Word/byte opcodes only, of course)----------------

OPC opLDRptrmll(){ LSptm(LSrll); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRptrmlr(){ LSptm(LSrlr); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRptrmar(){ LSptm(LSrar); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }
OPC opLDRptrmrr(){ LSptm(LSrrr); _RD=MMU->rdW(reg.tmp1); LSror; return 3; }