fet140_uart01_0115k.s43

MSP430系列单片机P140算法源代码集

#include  "msp430x12x.h"
;******************************************************************************
;   MSP-FET430P140 Demo - USART0 UART 115200 Echo ISR, HF XTAL ACLK
;
;   Description; Echo a received character, RX ISR used. Normal mode is LPM0, 
;   USART0 RX interrupt triggers TX Echo. Though not required, MCLK = LFXT1  
;   ACLK = MCLK = UCLK0 = LFXT1 = 8MHz 
;   Baud rate divider with 8MHz = 8000000/115200 = 0069 (0045h)
;   //*USART0 interrupt flags are in different SFR's from MSP430F14x/13x*// 
;   //*An external 8MHz XTAL on XIN XOUT is required for ACLK*//	  
;
;              
;                MSP430F149
;             -----------------
;         /|\|              XIN|-  
;          | |                 | 8MHz  
;          --|RST          XOUT|-
;            |                 |
;            |             P3.4|------------> 
;            |                 | 115200 - 8N1
;            |             P3.5|<------------
;
;   M.Buccini
;   Texas Instruments, Inc
;   January 2002
;******************************************************************************
;------------------------------------------------------------------------------ 
            ORG     01100h                  ; Progam Start 
;------------------------------------------------------------------------------ 
RESET       mov.w   #0A00h,SP               ; Initialize 'F149 stackpointer
            call    #Init_Sys               ;
                                            ;   
Mainloop    bis.b   #CPUOFF,SR              ; Enter LPM0
            nop                             ; Needed only for C-spy
                                            ;
;------------------------------------------------------------------------------ 
Init_Sys;   Initalize MSP430 system
;------------------------------------------------------------------------------ 
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupBC     bis.b   #XTS,&BCSCTL1           ; LFXT1 = HF XTAL
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag 
            mov.w   #0FFh,R15               ; R15 = Delay 
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start 
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set? 
            jnz     SetupOsc                ; OSC Fault, clear flag again 
            bis.b   #SELM1+SELM0,&BCSCTL2   ; MCLK = LFXT1
SetupUART0  mov.b   #CHAR,&UCTL0            ; 8-bit characters
            mov.b   #SSEL0,&UTCTL0          ; UCLK = ACLK
            mov.b   #045h,&UBR00            ; 8MHz 115200 
            mov.b   #000h,&UBR10            ; 8MHz 115200
            mov.b   #000h,&UMCTL0           ; 8MHz no modulation 115200
            bis.b   #UTXE0+URXE0,&ME1       ; Enable USART0 TXD/RXD
            bis.b   #URXIE0,&IE1            ; Enable USART0 RX interrupt
SetupP3     bis.b   #030h,&P3SEL            ; P3.4,5 = USART0 TXD/RXD
            bis.b   #010h,&P3DIR            ; P3.4 = output direction 
            eint                            ; General enable interrupts
            ret                             ; Return from subroutine
                                            ;             
;------------------------------------------------------------------------------ 
USART0RX_ISR;  Confirm TX buffer is ready, then Echo back RXed character
;------------------------------------------------------------------------------ 
TX1         bit.b   #UTXIFG0,&IFG1          ; USART0 TX buffer ready?
            jz      TX1                     ; Jump is TX buffer not ready
            mov.b   &RXBUF0,&TXBUF0         ; TX -> RXed character
            reti                            ; 
                                            ;
;------------------------------------------------------------------------------ 
;           Interrupt Vectors Used MSP430x13x/14x        
;------------------------------------------------------------------------------ 
            ORG     0FFFEh                  ; 
            DW      RESET                   ; POR, ext. Reset, Watchdog
            ORG     0FFF2h                  ; 
            DW      USART_ISR               ; USART0 receive
            end