ca0106.h

linux-2.6.15.6

						 * SPDIF Locked [21] For SPDIF channel only.
						 * Valid Audio [22] For SPDIF channel only.
						 */
#define CAPTURE_CONTROL         0x71            /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */
						/* Channel_id 0: 0x40c81000 must be changed to 0x40c80000 for SPDIF AC3 input or output. */
						/* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */
						/* Sample rate output control register Channel=0
						 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
						 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
						 * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source.
						 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
						 * Record mixer output enable [12:10] 
						 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
						 * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
						 * I2S output source select [18] (0=Audio from host, 1=Audio from SRC)
						 * Record mixer I2S enable [20:19] (enable/disable i2sin1 and i2sin0)
						 * I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.)
						 * I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.)
						 * I2S input mode [23] (0=Slave, 1=Master)
						 * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
						 * SPDIF output source select [26] (0=host, 1=SRC)
						 * Not used [27]
						 * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
						 * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
						 */ 
						/* Sample rate output control register Channel=1
						 * I2S Input 0 volume Right [7:0]
						 * I2S Input 0 volume Left [15:8]
						 * I2S Input 1 volume Right [23:16]
						 * I2S Input 1 volume Left [31:24]
						 */
						/* Sample rate output control register Channel=2
						 * SPDIF Input volume Right [23:16]
						 * SPDIF Input volume Left [31:24]
						 */
						/* Sample rate output control register Channel=3
						 * No used
						 */
#define SPDIF_SELECT2           0x72            /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */
#define ROUTING2_FRONT_MASK     0x00010000      /* Enable for Front speakers. */
#define ROUTING2_CENTER_LFE_MASK 0x00020000     /* Enable for Center/LFE speakers. */
#define ROUTING2_REAR_MASK      0x00080000      /* Enable for Rear speakers. */
						/* Audio output control
						 * AC97 output enable [5:0]
						 * I2S output enable [19:16]
						 * SPDIF output enable [27:24]
						 */ 
#define UNKNOWN73               0x73            /* Unknown. Readonly. Default 0x0 */
#define CHIP_VERSION            0x74            /* P17 Chip version. Channel_id 0 only. Default 00000071 */
#define EXTENDED_INT_MASK       0x75            /* Used by both playback and capture interrupt handler */
						/* Sets which Interrupts are enabled. */
						/* 0x00000001 = Half period. Playback.
						 * 0x00000010 = Full period. Playback.
						 * 0x00000100 = Half buffer. Playback.
						 * 0x00001000 = Full buffer. Playback.
						 * 0x00010000 = Half buffer. Capture.
						 * 0x00100000 = Full buffer. Capture.
						 * Capture can only do 2 periods.
						 * 0x01000000 = End audio. Playback.
						 * 0x40000000 = Half buffer Playback,Caputre xrun.
						 * 0x80000000 = Full buffer Playback,Caputre xrun.
						 */
#define EXTENDED_INT            0x76            /* Used by both playback and capture interrupt handler */
						/* Shows which interrupts are active at the moment. */
						/* Same bit layout as EXTENDED_INT_MASK */
#define COUNTER77               0x77		/* Counter range 0 to 0x3fffff, 192000 counts per second. */
#define COUNTER78               0x78		/* Counter range 0 to 0x3fffff, 44100 counts per second. */
#define EXTENDED_INT_TIMER      0x79            /* Channel_id 0 only. Used by both playback and capture interrupt handler */
						/* Causes interrupts based on timer intervals. */
#define SPI			0x7a		/* SPI: Serial Interface Register */
#define I2C_A			0x7b		/* I2C Address. 32 bit */
#define I2C_D0			0x7c		/* I2C Data Port 0. 32 bit */
#define I2C_D1			0x7d		/* I2C Data Port 1. 32 bit */
//I2C values
#define I2C_A_ADC_ADD_MASK	0x000000fe	//The address is a 7 bit address
#define I2C_A_ADC_RW_MASK	0x00000001	//bit mask for R/W
#define I2C_A_ADC_TRANS_MASK	0x00000010  	//Bit mask for I2c address DAC value
#define I2C_A_ADC_ABORT_MASK	0x00000020	//Bit mask for I2C transaction abort flag
#define I2C_A_ADC_LAST_MASK	0x00000040	//Bit mask for Last word transaction
#define I2C_A_ADC_BYTE_MASK	0x00000080	//Bit mask for Byte Mode

#define I2C_A_ADC_ADD		0x00000034	//This is the Device address for ADC 
#define I2C_A_ADC_READ		0x00000001	//To perform a read operation
#define I2C_A_ADC_START		0x00000100	//Start I2C transaction
#define I2C_A_ADC_ABORT		0x00000200	//I2C transaction abort
#define I2C_A_ADC_LAST		0x00000400	//I2C last transaction
#define I2C_A_ADC_BYTE		0x00000800	//I2C one byte mode

#define I2C_D_ADC_REG_MASK	0xfe000000  	//ADC address register 
#define I2C_D_ADC_DAT_MASK	0x01ff0000  	//ADC data register

#define ADC_TIMEOUT		0x00000007	//ADC Timeout Clock Disable
#define ADC_IFC_CTRL		0x0000000b	//ADC Interface Control
#define ADC_MASTER		0x0000000c	//ADC Master Mode Control
#define ADC_POWER		0x0000000d	//ADC PowerDown Control
#define ADC_ATTEN_ADCL		0x0000000e	//ADC Attenuation ADCL
#define ADC_ATTEN_ADCR		0x0000000f	//ADC Attenuation ADCR
#define ADC_ALC_CTRL1		0x00000010	//ADC ALC Control 1
#define ADC_ALC_CTRL2		0x00000011	//ADC ALC Control 2
#define ADC_ALC_CTRL3		0x00000012	//ADC ALC Control 3
#define ADC_NOISE_CTRL		0x00000013	//ADC Noise Gate Control
#define ADC_LIMIT_CTRL		0x00000014	//ADC Limiter Control
#define ADC_MUX			0x00000015  	//ADC Mux offset

#if 0
/* FIXME: Not tested yet. */
#define ADC_GAIN_MASK		0x000000ff	//Mask for ADC Gain
#define ADC_ZERODB		0x000000cf	//Value to set ADC to 0dB
#define ADC_MUTE_MASK		0x000000c0	//Mask for ADC mute
#define ADC_MUTE		0x000000c0	//Value to mute ADC
#define ADC_OSR			0x00000008	//Mask for ADC oversample rate select
#define ADC_TIMEOUT_DISABLE	0x00000008	//Value and mask to disable Timeout clock
#define ADC_HPF_DISABLE		0x00000100	//Value and mask to disable High pass filter
#define ADC_TRANWIN_MASK	0x00000070	//Mask for Length of Transient Window
#endif

#define ADC_MUX_MASK		0x0000000f	//Mask for ADC Mux
#define ADC_MUX_MIC		0x00000002	//Value to select Mic at ADC Mux
#define ADC_MUX_LINEIN		0x00000004	//Value to select LineIn at ADC Mux
#define ADC_MUX_PHONE		0x00000001	//Value to select TAD at ADC Mux (Not used)
#define ADC_MUX_AUX		0x00000008	//Value to select Aux at ADC Mux

#define SET_CHANNEL 0  /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
#define PCM_FRONT_CHANNEL 0
#define PCM_REAR_CHANNEL 1
#define PCM_CENTER_LFE_CHANNEL 2
#define PCM_UNKNOWN_CHANNEL 3
#define CONTROL_FRONT_CHANNEL 0
#define CONTROL_REAR_CHANNEL 3
#define CONTROL_CENTER_LFE_CHANNEL 1
#define CONTROL_UNKNOWN_CHANNEL 2

#include "ca_midi.h"

typedef struct snd_ca0106_channel ca0106_channel_t;
typedef struct snd_ca0106 ca0106_t;
typedef struct snd_ca0106_pcm ca0106_pcm_t;

struct snd_ca0106_channel {
	ca0106_t *emu;
	int number;
	int use;
	void (*interrupt)(ca0106_t *emu, ca0106_channel_t *channel);
	ca0106_pcm_t *epcm;
};

struct snd_ca0106_pcm {
	ca0106_t *emu;
	snd_pcm_substream_t *substream;
        int channel_id;
	unsigned short running;
};

typedef struct {
        u32 serial;
        char * name;
        int ac97;
	int gpio_type;
	int i2c_adc;
} ca0106_details_t;

// definition of the chip-specific record
struct snd_ca0106 {
	snd_card_t *card;
	ca0106_details_t *details;
	struct pci_dev *pci;

	unsigned long port;
	struct resource *res_port;
	int irq;

	unsigned int revision;		/* chip revision */
	unsigned int serial;            /* serial number */
	unsigned short model;		/* subsystem id */

	spinlock_t emu_lock;

	ac97_t *ac97;
	snd_pcm_t *pcm;

	ca0106_channel_t playback_channels[4];
	ca0106_channel_t capture_channels[4];
	u32 spdif_bits[4];             /* s/pdif out setup */
	int spdif_enable;
	int capture_source;
	int capture_mic_line_in;

	struct snd_dma_buffer buffer;

	ca_midi_t midi;
	ca_midi_t midi2;
};

int __devinit snd_ca0106_mixer(ca0106_t *emu);
int __devinit snd_ca0106_proc_init(ca0106_t * emu);

unsigned int snd_ca0106_ptr_read(ca0106_t * emu, 
					  unsigned int reg, 
					  unsigned int chn);

void snd_ca0106_ptr_write(ca0106_t *emu, 
				   unsigned int reg, 
				   unsigned int chn, 
				   unsigned int data);

int snd_ca0106_i2c_write(ca0106_t *emu, u32 reg, u32 value);