cs4281_hwdefs.h

linux-2.6.15.6

//****************************************************************************
//
// The following defines are for the flags in the I/O trap address and control
// registers for FM.
//
//****************************************************************************
#define IOTFM_SA_MASK                           0x0000FFFFL
#define IOTFM_MSK_MASK                          0x000F0000L
#define IOTFM_IODC_MASK                         0x06000000L
#define IOTFM_IODC_16_BIT                       0x00000000L
#define IOTFM_IODC_10_BIT                       0x02000000L
#define IOTFM_IODC_12_BIT                       0x04000000L
#define IOTFM_WSPI                              0x08000000L
#define IOTFM_RSPI                              0x10000000L
#define IOTFM_WSE                               0x20000000L
#define IOTFM_WE                                0x40000000L
#define IOTFM_RE                                0x80000000L
#define IOTFM_SA_SHIFT                          0L
#define IOTFM_MSK_SHIFT                         16L

//****************************************************************************
//
// The following defines are for the flags in the PC/PCI request register.
//
//****************************************************************************
#define PCPRR_RDC_MASK                         0x00000007L
#define PCPRR_REQ                              0x00008000L
#define PCPRR_RDC_SHIFT                        0L

//****************************************************************************
//
// The following defines are for the flags in the PC/PCI grant register.
//
//****************************************************************************
#define PCPGR_GDC_MASK                         0x00000007L
#define PCPGR_VL                               0x00008000L
#define PCPGR_GDC_SHIFT                        0L

//****************************************************************************
//
// The following defines are for the flags in the PC/PCI Control Register.
//
//****************************************************************************
#define PCPCR_EN                               0x00000001L

//****************************************************************************
//
// The following defines are for the flags in the debug index register.
//
//****************************************************************************
#define DREG_REGID_MASK                         0x0000007FL
#define DREG_DEBUG                              0x00000080L
#define DREG_RGBK_MASK                          0x00000700L
#define DREG_TRAP                               0x00000800L
#if !defined(NO_CS4612)
#if !defined(NO_CS4615)
#define DREG_TRAPX                              0x00001000L
#endif
#endif
#define DREG_REGID_SHIFT                        0L
#define DREG_RGBK_SHIFT                         8L
#define DREG_RGBK_REGID_MASK                    0x0000077FL
#define DREG_REGID_R0                           0x00000010L
#define DREG_REGID_R1                           0x00000011L
#define DREG_REGID_R2                           0x00000012L
#define DREG_REGID_R3                           0x00000013L
#define DREG_REGID_R4                           0x00000014L
#define DREG_REGID_R5                           0x00000015L
#define DREG_REGID_R6                           0x00000016L
#define DREG_REGID_R7                           0x00000017L
#define DREG_REGID_R8                           0x00000018L
#define DREG_REGID_R9                           0x00000019L
#define DREG_REGID_RA                           0x0000001AL
#define DREG_REGID_RB                           0x0000001BL
#define DREG_REGID_RC                           0x0000001CL
#define DREG_REGID_RD                           0x0000001DL
#define DREG_REGID_RE                           0x0000001EL
#define DREG_REGID_RF                           0x0000001FL
#define DREG_REGID_RA_BUS_LOW                   0x00000020L
#define DREG_REGID_RA_BUS_HIGH                  0x00000038L
#define DREG_REGID_YBUS_LOW                     0x00000050L
#define DREG_REGID_YBUS_HIGH                    0x00000058L
#define DREG_REGID_TRAP_0                       0x00000100L
#define DREG_REGID_TRAP_1                       0x00000101L
#define DREG_REGID_TRAP_2                       0x00000102L
#define DREG_REGID_TRAP_3                       0x00000103L
#define DREG_REGID_TRAP_4                       0x00000104L
#define DREG_REGID_TRAP_5                       0x00000105L
#define DREG_REGID_TRAP_6                       0x00000106L
#define DREG_REGID_TRAP_7                       0x00000107L
#define DREG_REGID_INDIRECT_ADDRESS             0x0000010EL
#define DREG_REGID_TOP_OF_STACK                 0x0000010FL
#if !defined(NO_CS4612)
#if !defined(NO_CS4615)
#define DREG_REGID_TRAP_8                       0x00000110L
#define DREG_REGID_TRAP_9                       0x00000111L
#define DREG_REGID_TRAP_10                      0x00000112L
#define DREG_REGID_TRAP_11                      0x00000113L
#define DREG_REGID_TRAP_12                      0x00000114L
#define DREG_REGID_TRAP_13                      0x00000115L
#define DREG_REGID_TRAP_14                      0x00000116L
#define DREG_REGID_TRAP_15                      0x00000117L
#define DREG_REGID_TRAP_16                      0x00000118L
#define DREG_REGID_TRAP_17                      0x00000119L
#define DREG_REGID_TRAP_18                      0x0000011AL
#define DREG_REGID_TRAP_19                      0x0000011BL
#define DREG_REGID_TRAP_20                      0x0000011CL
#define DREG_REGID_TRAP_21                      0x0000011DL
#define DREG_REGID_TRAP_22                      0x0000011EL
#define DREG_REGID_TRAP_23                      0x0000011FL
#endif
#endif
#define DREG_REGID_RSA0_LOW                     0x00000200L
#define DREG_REGID_RSA0_HIGH                    0x00000201L
#define DREG_REGID_RSA1_LOW                     0x00000202L
#define DREG_REGID_RSA1_HIGH                    0x00000203L
#define DREG_REGID_RSA2                         0x00000204L
#define DREG_REGID_RSA3                         0x00000205L
#define DREG_REGID_RSI0_LOW                     0x00000206L
#define DREG_REGID_RSI0_HIGH                    0x00000207L
#define DREG_REGID_RSI1                         0x00000208L
#define DREG_REGID_RSI2                         0x00000209L
#define DREG_REGID_SAGUSTATUS                   0x0000020AL
#define DREG_REGID_RSCONFIG01_LOW               0x0000020BL
#define DREG_REGID_RSCONFIG01_HIGH              0x0000020CL
#define DREG_REGID_RSCONFIG23_LOW               0x0000020DL
#define DREG_REGID_RSCONFIG23_HIGH              0x0000020EL
#define DREG_REGID_RSDMA01E                     0x0000020FL
#define DREG_REGID_RSDMA23E                     0x00000210L
#define DREG_REGID_RSD0_LOW                     0x00000211L
#define DREG_REGID_RSD0_HIGH                    0x00000212L
#define DREG_REGID_RSD1_LOW                     0x00000213L
#define DREG_REGID_RSD1_HIGH                    0x00000214L
#define DREG_REGID_RSD2_LOW                     0x00000215L
#define DREG_REGID_RSD2_HIGH                    0x00000216L
#define DREG_REGID_RSD3_LOW                     0x00000217L
#define DREG_REGID_RSD3_HIGH                    0x00000218L
#define DREG_REGID_SRAR_HIGH                    0x0000021AL
#define DREG_REGID_SRAR_LOW                     0x0000021BL
#define DREG_REGID_DMA_STATE                    0x0000021CL
#define DREG_REGID_CURRENT_DMA_STREAM           0x0000021DL
#define DREG_REGID_NEXT_DMA_STREAM              0x0000021EL
#define DREG_REGID_CPU_STATUS                   0x00000300L
#define DREG_REGID_MAC_MODE                     0x00000301L
#define DREG_REGID_STACK_AND_REPEAT             0x00000302L
#define DREG_REGID_INDEX0                       0x00000304L
#define DREG_REGID_INDEX1                       0x00000305L
#define DREG_REGID_DMA_STATE_0_3                0x00000400L
#define DREG_REGID_DMA_STATE_4_7                0x00000404L
#define DREG_REGID_DMA_STATE_8_11               0x00000408L
#define DREG_REGID_DMA_STATE_12_15              0x0000040CL
#define DREG_REGID_DMA_STATE_16_19              0x00000410L
#define DREG_REGID_DMA_STATE_20_23              0x00000414L
#define DREG_REGID_DMA_STATE_24_27              0x00000418L
#define DREG_REGID_DMA_STATE_28_31              0x0000041CL
#define DREG_REGID_DMA_STATE_32_35              0x00000420L
#define DREG_REGID_DMA_STATE_36_39              0x00000424L
#define DREG_REGID_DMA_STATE_40_43              0x00000428L
#define DREG_REGID_DMA_STATE_44_47              0x0000042CL
#define DREG_REGID_DMA_STATE_48_51              0x00000430L
#define DREG_REGID_DMA_STATE_52_55              0x00000434L
#define DREG_REGID_DMA_STATE_56_59              0x00000438L
#define DREG_REGID_DMA_STATE_60_63              0x0000043CL
#define DREG_REGID_DMA_STATE_64_67              0x00000440L
#define DREG_REGID_DMA_STATE_68_71              0x00000444L
#define DREG_REGID_DMA_STATE_72_75              0x00000448L
#define DREG_REGID_DMA_STATE_76_79              0x0000044CL
#define DREG_REGID_DMA_STATE_80_83              0x00000450L
#define DREG_REGID_DMA_STATE_84_87              0x00000454L
#define DREG_REGID_DMA_STATE_88_91              0x00000458L
#define DREG_REGID_DMA_STATE_92_95              0x0000045CL
#define DREG_REGID_TRAP_SELECT                  0x00000500L
#define DREG_REGID_TRAP_WRITE_0                 0x00000500L
#define DREG_REGID_TRAP_WRITE_1                 0x00000501L
#define DREG_REGID_TRAP_WRITE_2                 0x00000502L
#define DREG_REGID_TRAP_WRITE_3                 0x00000503L
#define DREG_REGID_TRAP_WRITE_4                 0x00000504L
#define DREG_REGID_TRAP_WRITE_5                 0x00000505L
#define DREG_REGID_TRAP_WRITE_6                 0x00000506L
#define DREG_REGID_TRAP_WRITE_7                 0x00000507L
#if !defined(NO_CS4612)
#if !defined(NO_CS4615)
#define DREG_REGID_TRAP_WRITE_8                 0x00000510L
#define DREG_REGID_TRAP_WRITE_9                 0x00000511L
#define DREG_REGID_TRAP_WRITE_10                0x00000512L
#define DREG_REGID_TRAP_WRITE_11                0x00000513L
#define DREG_REGID_TRAP_WRITE_12                0x00000514L
#define DREG_REGID_TRAP_WRITE_13                0x00000515L
#define DREG_REGID_TRAP_WRITE_14                0x00000516L
#define DREG_REGID_TRAP_WRITE_15                0x00000517L
#define DREG_REGID_TRAP_WRITE_16                0x00000518L
#define DREG_REGID_TRAP_WRITE_17                0x00000519L
#define DREG_REGID_TRAP_WRITE_18                0x0000051AL
#define DREG_REGID_TRAP_WRITE_19                0x0000051BL
#define DREG_REGID_TRAP_WRITE_20                0x0000051CL
#define DREG_REGID_TRAP_WRITE_21                0x0000051DL
#define DREG_REGID_TRAP_WRITE_22                0x0000051EL
#define DREG_REGID_TRAP_WRITE_23                0x0000051FL
#endif
#endif
#define DREG_REGID_MAC0_ACC0_LOW                0x00000600L
#define DREG_REGID_MAC0_ACC1_LOW                0x00000601L
#define DREG_REGID_MAC0_ACC2_LOW                0x00000602L
#define DREG_REGID_MAC0_ACC3_LOW                0x00000603L
#define DREG_REGID_MAC1_ACC0_LOW                0x00000604L
#define DREG_REGID_MAC1_ACC1_LOW                0x00000605L
#define DREG_REGID_MAC1_ACC2_LOW                0x00000606L
#define DREG_REGID_MAC1_ACC3_LOW                0x00000607L
#define DREG_REGID_MAC0_ACC0_MID                0x00000608L
#define DREG_REGID_MAC0_ACC1_MID                0x00000609L
#define DREG_REGID_MAC0_ACC2_MID                0x0000060AL
#define DREG_REGID_MAC0_ACC3_MID                0x0000060BL
#define DREG_REGID_MAC1_ACC0_MID                0x0000060CL
#define DREG_REGID_MAC1_ACC1_MID                0x0000060DL
#define DREG_REGID_MAC1_ACC2_MID                0x0000060EL
#define DREG_REGID_MAC1_ACC3_MID                0x0000060FL
#define DREG_REGID_MAC0_ACC0_HIGH               0x00000610L
#define DREG_REGID_MAC0_ACC1_HIGH               0x00000611L
#define DREG_REGID_MAC0_ACC2_HIGH               0x00000612L
#define DREG_REGID_MAC0_ACC3_HIGH               0x00000613L
#define DREG_REGID_MAC1_ACC0_HIGH               0x00000614L
#define DREG_REGID_MAC1_ACC1_HIGH               0x00000615L
#define DREG_REGID_MAC1_ACC2_HIGH               0x00000616L
#define DREG_REGID_MAC1_ACC3_HIGH               0x00000617L
#define DREG_REGID_RSHOUT_LOW                   0x00000620L
#define DREG_REGID_RSHOUT_MID                   0x00000628L
#define DREG_REGID_RSHOUT_HIGH                  0x00000630L

//****************************************************************************
//
// The following defines are for the flags in the AC97 S/PDIF Control register.
//
//****************************************************************************
#define SPDIF_CONTROL_SPDIF_EN                 0x00008000L
#define SPDIF_CONTROL_VAL                      0x00004000L
#define SPDIF_CONTROL_COPY                     0x00000004L
#define SPDIF_CONTROL_CC0                      0x00000010L
#define SPDIF_CONTROL_CC1                      0x00000020L
#define SPDIF_CONTROL_CC2                      0x00000040L
#define SPDIF_CONTROL_CC3                      0x00000080L
#define SPDIF_CONTROL_CC4                      0x00000100L
#define SPDIF_CONTROL_CC5                      0x00000200L
#define SPDIF_CONTROL_CC6                      0x00000400L
#define SPDIF_CONTROL_L                        0x00000800L

#endif // _H_HWDEFS