cs4281_hwdefs.h

linux-2.6.15.6

#define ACISV_ISV6                              0x00000008L
#define ACISV_ISV7                              0x00000010L
#define ACISV_ISV8                              0x00000020L
#define ACISV_ISV9                              0x00000040L
#define ACISV_ISV10                             0x00000080L
#define ACISV_ISV11                             0x00000100L
#define ACISV_ISV12                             0x00000200L

//****************************************************************************
//
// The following defines are for the flags in the AC97 status address
// register.
//
//****************************************************************************
#define ACSAD_SI_MASK                           0x0000007FL
#define ACSAD_SI_SHIFT                          0L

//****************************************************************************
//
// The following defines are for the flags in the AC97 status data register.
//
//****************************************************************************
#define ACSDA_SD_MASK                           0x0000FFFFL
#define ACSDA_SD_SHIFT                          0L

//****************************************************************************
//
// The following defines are for the flags in the I/O trap address and control
// registers (all 12).
//
//****************************************************************************
#define IOTAC_SA_MASK                           0x0000FFFFL
#define IOTAC_MSK_MASK                          0x000F0000L
#define IOTAC_IODC_MASK                         0x06000000L
#define IOTAC_IODC_16_BIT                       0x00000000L
#define IOTAC_IODC_10_BIT                       0x02000000L
#define IOTAC_IODC_12_BIT                       0x04000000L
#define IOTAC_WSPI                              0x08000000L
#define IOTAC_RSPI                              0x10000000L
#define IOTAC_WSE                               0x20000000L
#define IOTAC_WE                                0x40000000L
#define IOTAC_RE                                0x80000000L
#define IOTAC_SA_SHIFT                          0L
#define IOTAC_MSK_SHIFT                         16L

//****************************************************************************
//
// The following defines are for the flags in the PC/PCI master enable
// register.
//
//****************************************************************************
#define PCPCIEN_EN                              0x00000001L

//****************************************************************************
//
// The following defines are for the flags in the joystick poll/trigger
// register.
//
//****************************************************************************
#define JSPT_CAX                                0x00000001L
#define JSPT_CAY                                0x00000002L
#define JSPT_CBX                                0x00000004L
#define JSPT_CBY                                0x00000008L
#define JSPT_BA1                                0x00000010L
#define JSPT_BA2                                0x00000020L
#define JSPT_BB1                                0x00000040L
#define JSPT_BB2                                0x00000080L

//****************************************************************************
//
// The following defines are for the flags in the joystick control register.
// The TBF bit has been moved from MIDSR register to JSCTL register bit 8.
//
//****************************************************************************
#define JSCTL_SP_MASK                           0x00000003L
#define JSCTL_SP_SLOW                           0x00000000L
#define JSCTL_SP_MEDIUM_SLOW                    0x00000001L
#define JSCTL_SP_MEDIUM_FAST                    0x00000002L
#define JSCTL_SP_FAST                           0x00000003L
#define JSCTL_ARE                               0x00000004L
#define JSCTL_TBF                               0x00000100L


//****************************************************************************
//
// The following defines are for the flags in the MIDI control register.
//
//****************************************************************************
#define MIDCR_TXE                               0x00000001L
#define MIDCR_RXE                               0x00000002L
#define MIDCR_RIE                               0x00000004L
#define MIDCR_TIE                               0x00000008L
#define MIDCR_MLB                               0x00000010L
#define MIDCR_MRST                              0x00000020L

//****************************************************************************
//
// The following defines are for the flags in the MIDI status register.
//
//****************************************************************************
#define MIDSR_RBE                               0x00000080L
#define MIDSR_RDA                               0x00008000L

//****************************************************************************
//
// The following defines are for the flags in the MIDI write port register.
//
//****************************************************************************
#define MIDWP_MWD_MASK                          0x000000FFL
#define MIDWP_MWD_SHIFT                         0L

//****************************************************************************
//
// The following defines are for the flags in the MIDI read port register.
//
//****************************************************************************
#define MIDRP_MRD_MASK                          0x000000FFL
#define MIDRP_MRD_SHIFT                         0L

//****************************************************************************
//
// The following defines are for the flags in the configuration interface
// register.
//
//****************************************************************************
#define CFGI_CLK                                0x00000001L
#define CFGI_DOUT                               0x00000002L
#define CFGI_DIN_EEN                            0x00000004L
#define CFGI_EELD                               0x00000008L

//****************************************************************************
//
// The following defines are for the flags in the subsystem ID and vendor ID
// register.
//
//****************************************************************************
#define SSVID_VID_MASK                          0x0000FFFFL
#define SSVID_SID_MASK                          0xFFFF0000L
#define SSVID_VID_SHIFT                         0L
#define SSVID_SID_SHIFT                         16L

//****************************************************************************
//
// The following defines are for the flags in the GPIO pin interface register.
//
//****************************************************************************
#define GPIOR_VOLDN                             0x00000001L
#define GPIOR_VOLUP                             0x00000002L
#define GPIOR_SI2D                              0x00000004L
#define GPIOR_SI2OE                             0x00000008L

//****************************************************************************
//
// The following defines are for the flags in the AC97 status register 2.
//
//****************************************************************************
#define ACSTS2_CRDY                             0x00000001L
#define ACSTS2_VSTS                             0x00000002L

//****************************************************************************
//
// The following defines are for the flags in the AC97 input slot valid
// register 2.
//
//****************************************************************************
#define ACISV2_ISV3                             0x00000001L
#define ACISV2_ISV4                             0x00000002L
#define ACISV2_ISV5                             0x00000004L
#define ACISV2_ISV6                             0x00000008L
#define ACISV2_ISV7                             0x00000010L
#define ACISV2_ISV8                             0x00000020L
#define ACISV2_ISV9                             0x00000040L
#define ACISV2_ISV10                            0x00000080L
#define ACISV2_ISV11                            0x00000100L
#define ACISV2_ISV12                            0x00000200L

//****************************************************************************
//
// The following defines are for the flags in the AC97 status address
// register 2.
//
//****************************************************************************
#define ACSAD2_SI_MASK                          0x0000007FL
#define ACSAD2_SI_SHIFT                         0L

//****************************************************************************
//
// The following defines are for the flags in the AC97 status data register 2.
//
//****************************************************************************
#define ACSDA2_SD_MASK                          0x0000FFFFL
#define ACSDA2_SD_SHIFT                         0L

//****************************************************************************
//
// The following defines are for the flags in the I/O trap control register.
//
//****************************************************************************
#define IOTCR_ITD                               0x00000001L
#define IOTCR_HRV                               0x00000002L
#define IOTCR_SRV                               0x00000004L
#define IOTCR_DTI                               0x00000008L
#define IOTCR_DFI                               0x00000010L
#define IOTCR_DDP                               0x00000020L
#define IOTCR_JTE                               0x00000040L
#define IOTCR_PPE                               0x00000080L

//****************************************************************************
//
// The following defines are for the flags in the I/O trap address and control
// registers for Hardware Master Volume.  
//
//****************************************************************************
#define IOTGP_SA_MASK                           0x0000FFFFL
#define IOTGP_MSK_MASK                          0x000F0000L
#define IOTGP_IODC_MASK                         0x06000000L
#define IOTGP_IODC_16_BIT                       0x00000000L
#define IOTGP_IODC_10_BIT                       0x02000000L
#define IOTGP_IODC_12_BIT                       0x04000000L
#define IOTGP_WSPI                              0x08000000L
#define IOTGP_RSPI                              0x10000000L
#define IOTGP_WSE                               0x20000000L
#define IOTGP_WE                                0x40000000L
#define IOTGP_RE                                0x80000000L
#define IOTGP_SA_SHIFT                          0L
#define IOTGP_MSK_SHIFT                         16L

//****************************************************************************
//
// The following defines are for the flags in the I/O trap address and control
// registers for Sound Blaster
//
//****************************************************************************
#define IOTSB_SA_MASK                           0x0000FFFFL
#define IOTSB_MSK_MASK                          0x000F0000L
#define IOTSB_IODC_MASK                         0x06000000L
#define IOTSB_IODC_16_BIT                       0x00000000L
#define IOTSB_IODC_10_BIT                       0x02000000L
#define IOTSB_IODC_12_BIT                       0x04000000L
#define IOTSB_WSPI                              0x08000000L
#define IOTSB_RSPI                              0x10000000L
#define IOTSB_WSE                               0x20000000L
#define IOTSB_WE                                0x40000000L
#define IOTSB_RE                                0x80000000L
#define IOTSB_SA_SHIFT                          0L
#define IOTSB_MSK_SHIFT                         16L