cs4281_hwdefs.h

linux-2.6.15.6

#define IOTCR_DMA0                              0x00000000L
#define IOTCR_DMA1                              0x00000400L
#define IOTCR_DMA2                              0x00000800L
#define IOTCR_DMA3                              0x00000C00L
#define IOTCR_CCLS                              0x00000100L
#define IOTCR_PCPCI                             0x00000200L
#define IOTCR_DDMA                              0x00000300L

#define SBWBS_WBB                               0x00000080L

//****************************************************************************
//
// The following defines are for the flags in the SRC Slot Assignment Register
// (SRCSA)
//
//****************************************************************************
#define SRCSA_PLSS_MASK                         0x0000001FL
#define SRCSA_PLSS_SHIFT                        0L
#define SRCSA_PRSS_MASK                         0x00001F00L
#define SRCSA_PRSS_SHIFT                        8L
#define SRCSA_CLSS_MASK                         0x001F0000L
#define SRCSA_CLSS_SHIFT                        16L
#define SRCSA_CRSS_MASK                         0x1F000000L
#define SRCSA_CRSS_SHIFT                        24L

//****************************************************************************
//
// The following defines are for the flags in the Sound System Power Management
// register.(SSPM)
//
//****************************************************************************
#define SSPM_FPDN                               0x00000080L
#define SSPM_MIXEN                              0x00000040L
#define SSPM_CSRCEN                             0x00000020L
#define SSPM_PSRCEN                             0x00000010L
#define SSPM_JSEN                               0x00000008L
#define SSPM_ACLEN                              0x00000004L
#define SSPM_FMEN                               0x00000002L

//****************************************************************************
//
// The following defines are for the flags in the Sound System Control
// Register. (SSCR)
//
//****************************************************************************
#define SSCR_SB                                 0x00000004L
#define SSCR_HVC                                0x00000008L
#define SSCR_LPFIFO                             0x00000040L
#define SSCR_LPSRC                              0x00000080L
#define SSCR_XLPSRC                             0x00000100L
#define SSCR_MVMD                               0x00010000L
#define SSCR_MVAD                               0x00020000L
#define SSCR_MVLD                               0x00040000L
#define SSCR_MVCS                               0x00080000L

//****************************************************************************
//
// The following defines are for the flags in the Clock Control Register 1. 
// (CLKCR1)
//
//****************************************************************************
#define CLKCR1_DLLSS_MASK                       0x0000000CL
#define CLKCR1_DLLSS_SHIFT                      2L
#define CLKCR1_DLLP                             0x00000010L
#define CLKCR1_SWCE                             0x00000020L
#define CLKCR1_DLLOS                            0x00000040L
#define CLKCR1_CKRA                             0x00010000L
#define CLKCR1_CKRN                             0x00020000L
#define CLKCR1_DLLRDY                           0x01000000L
#define CLKCR1_CLKON                            0x02000000L

//****************************************************************************
//
// The following defines are for the flags in the Sound Blaster Read Buffer
// Status.(SBRBS)
//
//****************************************************************************
#define SBRBS_RD_MASK                           0x0000007FL
#define SBRBS_RD_SHIFT                          0L
#define SBRBS_RBF                               0x00000080L

//****************************************************************************
//
// The following defines are for the flags in the serial port master control
// register.(SERMC)
//
//****************************************************************************
#define SERMC_MSPE                              0x00000001L
#define SERMC_PTC_MASK                          0x0000000EL
#define SERMC_PTC_SHIFT                         1L
#define SERMC_PTC_AC97                          0x00000002L
#define SERMC_PLB                               0x00000010L
#define SERMC_PXLB                              0x00000020L
#define SERMC_LOFV                              0x00080000L
#define SERMC_SLB                               0x00100000L
#define SERMC_SXLB                              0x00200000L
#define SERMC_ODSEN1                            0x01000000L
#define SERMC_ODSEN2                            0x02000000L

//****************************************************************************
//
// The following defines are for the flags in the General Purpose I/O Register. 
// (GPIOR)
//
//****************************************************************************
#define GPIOR_VDNS                              0x00000001L
#define GPIOR_VUPS                              0x00000002L
#define GPIOR_GP1S                              0x00000004L
#define GPIOR_GP3S                              0x00000008L
#define GPIOR_GPSS                              0x00000010L
#define GPIOR_GPPS                              0x00000020L
#define GPIOR_GP1D                              0x00000400L
#define GPIOR_GP3D                              0x00000800L
#define GPIOR_VDNLT                             0x00010000L
#define GPIOR_VDNPO                             0x00020000L
#define GPIOR_VDNST                             0x00040000L
#define GPIOR_VDNW                              0x00080000L
#define GPIOR_VUPLT                             0x00100000L
#define GPIOR_VUPPO                             0x00200000L
#define GPIOR_VUPST                             0x00400000L
#define GPIOR_VUPW                              0x00800000L
#define GPIOR_GP1OE                             0x01000000L
#define GPIOR_GP1PT                             0x02000000L
#define GPIOR_GP1ST                             0x04000000L
#define GPIOR_GP1W                              0x08000000L
#define GPIOR_GP3OE                             0x10000000L
#define GPIOR_GP3PT                             0x20000000L
#define GPIOR_GP3ST                             0x40000000L
#define GPIOR_GP3W                              0x80000000L

//****************************************************************************
//
// The following defines are for the flags in the clock control register 1.
//
//****************************************************************************
#define CLKCR1_PLLSS_MASK                       0x0000000CL
#define CLKCR1_PLLSS_SERIAL                     0x00000000L
#define CLKCR1_PLLSS_CRYSTAL                    0x00000004L
#define CLKCR1_PLLSS_PCI                        0x00000008L
#define CLKCR1_PLLSS_RESERVED                   0x0000000CL
#define CLKCR1_PLLP                             0x00000010L
#define CLKCR1_SWCE                             0x00000020L
#define CLKCR1_PLLOS                            0x00000040L

//****************************************************************************
//
// The following defines are for the flags in the feature reporting register.
//
//****************************************************************************
#define FRR_FAB_MASK                            0x00000003L
#define FRR_MASK_MASK                           0x0000001CL
#define FRR_ID_MASK                             0x00003000L
#define FRR_FAB_SHIFT                           0L
#define FRR_MASK_SHIFT                          2L
#define FRR_ID_SHIFT                            12L

//****************************************************************************
//
// The following defines are for the flags in the serial port 1 configuration
// register.
//
//****************************************************************************
#define SERC1_VALUE                             0x00000003L
#define SERC1_SO1EN                             0x00000001L
#define SERC1_SO1F_MASK                         0x0000000EL
#define SERC1_SO1F_CS423X                       0x00000000L
#define SERC1_SO1F_AC97                         0x00000002L
#define SERC1_SO1F_DAC                          0x00000004L
#define SERC1_SO1F_SPDIF                        0x00000006L

//****************************************************************************
//
// The following defines are for the flags in the serial port 2 configuration
// register.
//
//****************************************************************************
#define SERC2_VALUE                             0x00000003L
#define SERC2_SI1EN                             0x00000001L
#define SERC2_SI1F_MASK                         0x0000000EL
#define SERC2_SI1F_CS423X                       0x00000000L
#define SERC2_SI1F_AC97                         0x00000002L
#define SERC2_SI1F_ADC                          0x00000004L
#define SERC2_SI1F_SPDIF                        0x00000006L

//****************************************************************************
//
// The following defines are for the flags in the AC97 control register.
//
//****************************************************************************
#define ACCTL_ESYN                              0x00000002L
#define ACCTL_VFRM                              0x00000004L
#define ACCTL_DCV                               0x00000008L
#define ACCTL_CRW                               0x00000010L
#define ACCTL_TC                                0x00000040L

//****************************************************************************
//
// The following defines are for the flags in the AC97 status register.
//
//****************************************************************************
#define ACSTS_CRDY                              0x00000001L
#define ACSTS_VSTS                              0x00000002L

//****************************************************************************
//
// The following defines are for the flags in the AC97 output slot valid
// register.
//
//****************************************************************************
#define ACOSV_SLV3                              0x00000001L
#define ACOSV_SLV4                              0x00000002L
#define ACOSV_SLV5                              0x00000004L
#define ACOSV_SLV6                              0x00000008L
#define ACOSV_SLV7                              0x00000010L
#define ACOSV_SLV8                              0x00000020L
#define ACOSV_SLV9                              0x00000040L
#define ACOSV_SLV10                             0x00000080L
#define ACOSV_SLV11                             0x00000100L
#define ACOSV_SLV12                             0x00000200L

//****************************************************************************
//
// The following defines are for the flags in the AC97 command address
// register.
//
//****************************************************************************
#define ACCAD_CI_MASK                           0x0000007FL
#define ACCAD_CI_SHIFT                          0L

//****************************************************************************
//
// The following defines are for the flags in the AC97 command data register.
//
//****************************************************************************
#define ACCDA_CD_MASK                           0x0000FFFFL
#define ACCDA_CD_SHIFT                          0L

//****************************************************************************
//
// The following defines are for the flags in the AC97 input slot valid
// register.
//
//****************************************************************************
#define ACISV_ISV3                              0x00000001L
#define ACISV_ISV4                              0x00000002L
#define ACISV_ISV5                              0x00000004L