cs4281_hwdefs.h

linux-2.6.15.6

#define BA0_AC97_VENDOR_ID2                     0x0000107EL

//****************************************************************************
//
// The following define the offsets of the registers and memories accessed via
// base address register one on the CS4281 part.
//
//****************************************************************************

//****************************************************************************
//
// The following defines are for the flags in the PCI device ID/vendor ID
// register.
//
//****************************************************************************
#define PDV_VENID_MASK                          0x0000FFFFL
#define PDV_DEVID_MASK                          0xFFFF0000L
#define PDV_VENID_SHIFT                         0L
#define PDV_DEVID_SHIFT                         16L
#define VENID_CIRRUS_LOGIC                      0x1013L
#define DEVID_CS4281                            0x6005L

//****************************************************************************
//
// The following defines are for the flags in the PCI status and command
// register.
//
//****************************************************************************
#define PSC_IO_SPACE_ENABLE                     0x00000001L
#define PSC_MEMORY_SPACE_ENABLE                 0x00000002L
#define PSC_BUS_MASTER_ENABLE                   0x00000004L
#define PSC_SPECIAL_CYCLES                      0x00000008L
#define PSC_MWI_ENABLE                          0x00000010L
#define PSC_VGA_PALETTE_SNOOP                   0x00000020L
#define PSC_PARITY_RESPONSE                     0x00000040L
#define PSC_WAIT_CONTROL                        0x00000080L
#define PSC_SERR_ENABLE                         0x00000100L
#define PSC_FAST_B2B_ENABLE                     0x00000200L
#define PSC_UDF_MASK                            0x007F0000L
#define PSC_FAST_B2B_CAPABLE                    0x00800000L
#define PSC_PARITY_ERROR_DETECTED               0x01000000L
#define PSC_DEVSEL_TIMING_MASK                  0x06000000L
#define PSC_TARGET_ABORT_SIGNALLED              0x08000000L
#define PSC_RECEIVED_TARGET_ABORT               0x10000000L
#define PSC_RECEIVED_MASTER_ABORT               0x20000000L
#define PSC_SIGNALLED_SERR                      0x40000000L
#define PSC_DETECTED_PARITY_ERROR               0x80000000L
#define PSC_UDF_SHIFT                           16L
#define PSC_DEVSEL_TIMING_SHIFT                 25L

//****************************************************************************
//
// The following defines are for the flags in the PCI class/revision ID
// register.
//
//****************************************************************************
#define PCR_REVID_MASK                          0x000000FFL
#define PCR_INTERFACE_MASK                      0x0000FF00L
#define PCR_SUBCLASS_MASK                       0x00FF0000L
#define PCR_CLASS_MASK                          0xFF000000L
#define PCR_REVID_SHIFT                         0L
#define PCR_INTERFACE_SHIFT                     8L
#define PCR_SUBCLASS_SHIFT                      16L
#define PCR_CLASS_SHIFT                         24L

//****************************************************************************
//
// The following defines are for the flags in the PCI latency timer register.
//
//****************************************************************************
#define PLT_CACHE_LINE_SIZE_MASK                0x000000FFL
#define PLT_LATENCY_TIMER_MASK                  0x0000FF00L
#define PLT_HEADER_TYPE_MASK                    0x00FF0000L
#define PLT_BIST_MASK                           0xFF000000L
#define PLT_CACHE_LINE_SIZE_SHIFT               0L
#define PLT_LATENCY_TIMER_SHIFT                 8L
#define PLT_HEADER_TYPE_SHIFT                   16L
#define PLT_BIST_SHIFT                          24L

//****************************************************************************
//
// The following defines are for the flags in the PCI base address registers.
//
//****************************************************************************
#define PBAR_MEMORY_SPACE_INDICATOR             0x00000001L
#define PBAR_LOCATION_TYPE_MASK                 0x00000006L
#define PBAR_NOT_PREFETCHABLE                   0x00000008L
#define PBAR_ADDRESS_MASK                       0xFFFFFFF0L
#define PBAR_LOCATION_TYPE_SHIFT                1L

//****************************************************************************
//
// The following defines are for the flags in the PCI subsystem ID/subsystem
// vendor ID register.
//
//****************************************************************************
#define PSS_SUBSYSTEM_VENDOR_ID_MASK            0x0000FFFFL
#define PSS_SUBSYSTEM_ID_MASK                   0xFFFF0000L
#define PSS_SUBSYSTEM_VENDOR_ID_SHIFT           0L
#define PSS_SUBSYSTEM_ID_SHIFT                  16L

//****************************************************************************
//
// The following defines are for the flags in the PCI interrupt register.
//
//****************************************************************************
#define PI_LINE_MASK                            0x000000FFL
#define PI_PIN_MASK                             0x0000FF00L
#define PI_MIN_GRANT_MASK                       0x00FF0000L
#define PI_MAX_LATENCY_MASK                     0xFF000000L
#define PI_LINE_SHIFT                           0L
#define PI_PIN_SHIFT                            8L
#define PI_MIN_GRANT_SHIFT                      16L
#define PI_MAX_LATENCY_SHIFT                    24L

//****************************************************************************
//
// The following defines are for the flags in the host interrupt status
// register.
//
//****************************************************************************
#define HISR_HVOLMASK                            0x00000003L
#define HISR_VDNI                                0x00000001L
#define HISR_VUPI                                0x00000002L
#define HISR_GP1I                                0x00000004L
#define HISR_GP3I                                0x00000008L
#define HISR_GPSI                                0x00000010L
#define HISR_GPPI                                0x00000020L
#define HISR_DMAI                                0x00040000L
#define HISR_FIFOI                               0x00100000L
#define HISR_HVOL                                0x00200000L
#define HISR_MIDI                                0x00400000L
#define HISR_SBINT                               0x00800000L
#define HISR_INTENA                              0x80000000L
#define HISR_DMA_MASK                            0x00000F00L
#define HISR_FIFO_MASK                           0x0000F000L
#define HISR_DMA_SHIFT                           8L
#define HISR_FIFO_SHIFT                          12L
#define HISR_FIFO0                               0x00001000L
#define HISR_FIFO1                               0x00002000L
#define HISR_FIFO2                               0x00004000L
#define HISR_FIFO3                               0x00008000L
#define HISR_DMA0                                0x00000100L
#define HISR_DMA1                                0x00000200L
#define HISR_DMA2                                0x00000400L
#define HISR_DMA3                                0x00000800L
#define HISR_RESERVED                            0x40000000L

//****************************************************************************
//
// The following defines are for the flags in the host interrupt control
// register.
//
//****************************************************************************
#define HICR_IEV                                 0x00000001L
#define HICR_CHGM                                0x00000002L

//****************************************************************************
//
// The following defines are for the flags in the DMA Mode Register n
// (DMRn)
//
//****************************************************************************
#define DMRn_TR_MASK                             0x0000000CL
#define DMRn_TR_SHIFT                            2L
#define DMRn_AUTO                                0x00000010L
#define DMRn_TR_READ                             0x00000008L
#define DMRn_TR_WRITE                            0x00000004L
#define DMRn_TYPE_MASK                           0x000000C0L
#define DMRn_TYPE_SHIFT                          6L
#define DMRn_SIZE8                               0x00010000L
#define DMRn_MONO                                0x00020000L
#define DMRn_BEND                                0x00040000L
#define DMRn_USIGN                               0x00080000L
#define DMRn_SIZE20                              0x00100000L
#define DMRn_SWAPC                               0x00400000L
#define DMRn_CBC                                 0x01000000L
#define DMRn_TBC                                 0x02000000L
#define DMRn_POLL                                0x10000000L
#define DMRn_DMA                                 0x20000000L
#define DMRn_FSEL_MASK                           0xC0000000L
#define DMRn_FSEL_SHIFT                          30L
#define DMRn_FSEL0                               0x00000000L
#define DMRn_FSEL1                               0x40000000L
#define DMRn_FSEL2                               0x80000000L
#define DMRn_FSEL3                               0xC0000000L

//****************************************************************************
//
// The following defines are for the flags in the DMA Command Register n
// (DCRn)
//
//****************************************************************************
#define DCRn_HTCIE                               0x00020000L
#define DCRn_TCIE                                0x00010000L
#define DCRn_MSK                                 0x00000001L

//****************************************************************************
//
// The following defines are for the flags in the FIFO Control 
// register n.(FCRn)
//
//****************************************************************************
#define FCRn_OF_MASK                            0x0000007FL
#define FCRn_OF_SHIFT                           0L
#define FCRn_SZ_MASK                            0x00007F00L
#define FCRn_SZ_SHIFT                           8L
#define FCRn_LS_MASK                            0x001F0000L
#define FCRn_LS_SHIFT                           16L
#define FCRn_RS_MASK                            0x1F000000L
#define FCRn_RS_SHIFT                           24L
#define FCRn_FEN                                0x80000000L
#define FCRn_PSH                                0x20000000L
#define FCRn_DACZ                               0x40000000L

//****************************************************************************
//
// The following defines are for the flags in the serial port Power Management
// control register.(SPMC)
//
//****************************************************************************
#define SPMC_RSTN                               0x00000001L
#define SPMC_ASYN                               0x00000002L
#define SPMC_WUP1                               0x00000004L
#define SPMC_WUP2                               0x00000008L
#define SPMC_ASDI2E                             0x00000100L
#define SPMC_ESSPD                              0x00000200L
#define SPMC_GISPEN                             0x00004000L
#define SPMC_GIPPEN                             0x00008000L

//****************************************************************************
//
// The following defines are for the flags in the Configuration Load register.
// (CFLR)
//
//****************************************************************************
#define CFLR_CLOCK_SOURCE_MASK                  0x00000003L
#define CFLR_CLOCK_SOURCE_AC97                  0x00000001L

#define CFLR_CB0_MASK                            0x000000FFL
#define CFLR_CB1_MASK                            0x0000FF00L
#define CFLR_CB2_MASK                            0x00FF0000L
#define CFLR_CB3_MASK                            0xFF000000L
#define CFLR_CB0_SHIFT                           0L
#define CFLR_CB1_SHIFT                           8L
#define CFLR_CB2_SHIFT                           16L
#define CFLR_CB3_SHIFT                           24L