📄 prcm.h
字号:
/* * prcm.h - Access definations for use in OMAP24XX clock and power management * * Copyright (C) 2005 Texas Instruments, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */#ifndef __ASM_ARM_ARCH_DPM_PRCM_H#define __ASM_ARM_ARCH_DPM_PRCM_H/* SET_PERFORMANCE_LEVEL PARAMETERS */#define PRCM_HALF_SPEED 1#define PRCM_FULL_SPEED 2#ifndef __ASSEMBLER__#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))#define PRCM_REVISION PRCM_REG32(0x000)#define PRCM_SYSCONFIG PRCM_REG32(0x010)#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)#define PRCM_VOLTCTRL PRCM_REG32(0x050)#define PRCM_VOLTST PRCM_REG32(0x054)#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)#define PRCM_VOLTSETUP PRCM_REG32(0x090)#define PRCM_CLKSSETUP PRCM_REG32(0x094)#define PRCM_POLCTRL PRCM_REG32(0x098)/* GENERAL PURPOSE */#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)/* MPU */#define CM_CLKSEL_MPU PRCM_REG32(0x140)#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)#define RM_RSTST_MPU PRCM_REG32(0x158)#define PM_WKDEP_MPU PRCM_REG32(0x1C8)#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)#define PM_PWSTST_MPU PRCM_REG32(0x1E4)/* CORE */#define CM_FCLKEN1_CORE PRCM_REG32(0x200)#define CM_FCLKEN2_CORE PRCM_REG32(0x204)#define CM_FCLKEN3_CORE PRCM_REG32(0x208)#define CM_ICLKEN1_CORE PRCM_REG32(0x210)#define CM_ICLKEN2_CORE PRCM_REG32(0x214)#define CM_ICLKEN3_CORE PRCM_REG32(0x218)#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)#define CM_IDLEST1_CORE PRCM_REG32(0x220)#define CM_IDLEST2_CORE PRCM_REG32(0x224)#define CM_IDLEST3_CORE PRCM_REG32(0x228)#define CM_IDLEST4_CORE PRCM_REG32(0x22C)#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)#define CM_CLKSEL1_CORE PRCM_REG32(0x240)#define CM_CLKSEL2_CORE PRCM_REG32(0x244)#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)#define PM_WKEN1_CORE PRCM_REG32(0x2A0)#define PM_WKEN2_CORE PRCM_REG32(0x2A4)#define PM_WKST1_CORE PRCM_REG32(0x2B0)#define PM_WKST2_CORE PRCM_REG32(0x2B4)#define PM_WKDEP_CORE PRCM_REG32(0x2C8)#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)#define PM_PWSTST_CORE PRCM_REG32(0x2E4)/* GFX */#define CM_FCLKEN_GFX PRCM_REG32(0x300)#define CM_ICLKEN_GFX PRCM_REG32(0x310)#define CM_IDLEST_GFX PRCM_REG32(0x320)#define CM_CLKSEL_GFX PRCM_REG32(0x340)#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)#define RM_RSTCTRL_GFX PRCM_REG32(0x350)#define RM_RSTST_GFX PRCM_REG32(0x358)#define PM_WKDEP_GFX PRCM_REG32(0x3C8)#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)#define PM_PWSTST_GFX PRCM_REG32(0x3E4)/* WAKE-UP */#define CM_FCLKEN_WKUP PRCM_REG32(0x400)#define CM_ICLKEN_WKUP PRCM_REG32(0x410)#define CM_IDLEST_WKUP PRCM_REG32(0x420)#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)#define CM_CLKSEL_WKUP PRCM_REG32(0x440)#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)#define RM_RSTTIME_WKUP PRCM_REG32(0x454)#define RM_RSTST_WKUP PRCM_REG32(0x458)#define PM_WKEN_WKUP PRCM_REG32(0x4A0)#define PM_WKST_WKUP PRCM_REG32(0x4B0)/* CLOCKS */#define CM_CLKEN_PLL PRCM_REG32(0x500)#define CM_IDLEST_CKGEN PRCM_REG32(0x520)#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)#define CM_CLKSEL1_PLL PRCM_REG32(0x540)#define CM_CLKSEL2_PLL PRCM_REG32(0x544)/* DSP */#define CM_FCLKEN_DSP PRCM_REG32(0x800)#define CM_ICLKEN_DSP PRCM_REG32(0x810)#define CM_IDLEST_DSP PRCM_REG32(0x820)#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)#define CM_CLKSEL_DSP PRCM_REG32(0x840)#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)#define RM_RSTCTRL_DSP PRCM_REG32(0x850)#define RM_RSTST_DSP PRCM_REG32(0x858)#define PM_WKEN_DSP PRCM_REG32(0x8A0)#define PM_WKDEP_DSP PRCM_REG32(0x8C8)#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)#define PM_PWSTST_DSP PRCM_REG32(0x8E4)#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)/* IVA */#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)/* Modem on 2430 */#define CM_FCLKEN_MDM PRCM_REG32(0xC00)#define CM_ICLKEN_MDM PRCM_REG32(0xC10)#define CM_IDLEST_MDM PRCM_REG32(0xC20)#define CM_CLKSEL_MDM PRCM_REG32(0xC40)/* FIXME: Move to header for 2430 */#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000)#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)#define GPMC_BASE (OMAP24XX_GPMC_BASE)#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset))#define GPT1_BASE (OMAP24XX_GPT1)#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))/* Misc sysconfig */#define DISPC_SYSCONFIG DISP_REG32(0x410)#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000)#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10)//#define DSP_MMU_SYSCONFIG 0x5A000010#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10)//#define IVA_MMU_SYSCONFIG 0x5D000010//#define DSP_DMA_SYSCONFIG 0x00FCC02C#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)#define GPMC_SYSCONFIG GPMC_REG32(0x010)#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010)#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054)#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054)#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054)//#define IVA_SYSCONFIG 0x5C060010#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10)#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10)#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010)//#define VLYNQ_SYSCONFIG 0x67FFFE10/* rkw - good cannidates for PM_ to start what nm was trying */#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -