platform.h

linux-2.6.15.6

#define VERSATILE_SYS_LED7             (1 << 7)

#define ALL_LEDS                  0xFF

#define LED_BANK                  VERSATILE_SYS_LED

/* 
 * Control registers
 */
#define VERSATILE_IDFIELD_OFFSET	0x0	/* Versatile build information */
#define VERSATILE_FLASHPROG_OFFSET	0x4	/* Flash devices */
#define VERSATILE_INTREG_OFFSET		0x8	/* Interrupt control */
#define VERSATILE_DECODE_OFFSET		0xC	/* Fitted logic modules */


/* ------------------------------------------------------------------------
 *  Versatile Interrupt Controller - control registers
 * ------------------------------------------------------------------------
 * 
 *  Offsets from interrupt controller base 
 * 
 *  System Controller interrupt controller base is
 * 
 * 	VERSATILE_IC_BASE
 * 
 *  Core Module interrupt controller base is
 * 
 * 	VERSATILE_SYS_IC 
 * 
 */
#define VIC_IRQ_STATUS                  0
#define VIC_FIQ_STATUS                  0x04
#define VIC_IRQ_RAW_STATUS              0x08
#define VIC_INT_SELECT                  0x0C	/* 1 = FIQ, 0 = IRQ */
#define VIC_IRQ_ENABLE                  0x10	/* 1 = enable, 0 = disable */
#define VIC_IRQ_ENABLE_CLEAR            0x14
#define VIC_IRQ_SOFT                    0x18
#define VIC_IRQ_SOFT_CLEAR              0x1C
#define VIC_PROTECT                     0x20
#define VIC_VECT_ADDR                   0x30
#define VIC_DEF_VECT_ADDR               0x34
#define VIC_VECT_ADDR0                  0x100	/* 0 to 15 */
#define VIC_VECT_CNTL0                  0x200	/* 0 to 15 */
#define VIC_ITCR                        0x300   /* VIC test control register */

#define VIC_FIQ_RAW_STATUS              0x08
#define VIC_FIQ_ENABLE                  0x10	/* 1 = enable, 0 = disable */
#define VIC_FIQ_ENABLE_CLEAR            0x14
#define VIC_FIQ_SOFT                    0x18
#define VIC_FIQ_SOFT_CLEAR              0x1C

#define SIC_IRQ_STATUS                  0
#define SIC_IRQ_RAW_STATUS              0x04
#define SIC_IRQ_ENABLE                  0x08
#define SIC_IRQ_ENABLE_SET              0x08
#define SIC_IRQ_ENABLE_CLEAR            0x0C
#define SIC_INT_SOFT_SET                0x10
#define SIC_INT_SOFT_CLEAR              0x14
#define SIC_INT_PIC_ENABLE              0x20	/* read status of pass through mask */
#define SIC_INT_PIC_ENABLES             0x20	/* set interrupt pass through bits */
#define SIC_INT_PIC_ENABLEC             0x24	/* Clear interrupt pass through bits */

#define VICVectCntl_Enable		(1 << 5)

/* ------------------------------------------------------------------------
 *  Interrupts - bit assignment (primary)
 * ------------------------------------------------------------------------
 */

#define INT_WDOGINT                     0	/* Watchdog timer */
#define INT_SOFTINT                     1	/* Software interrupt */
#define INT_COMMRx                      2	/* Debug Comm Rx interrupt */
#define INT_COMMTx                      3	/* Debug Comm Tx interrupt */
#define INT_TIMERINT0_1                 4	/* Timer 0 and 1 */
#define INT_TIMERINT2_3                 5	/* Timer 2 and 3 */
#define INT_GPIOINT0                    6	/* GPIO 0 */
#define INT_GPIOINT1                    7	/* GPIO 1 */
#define INT_GPIOINT2                    8	/* GPIO 2 */
#define INT_GPIOINT3                    9	/* GPIO 3 */
#define INT_RTCINT                      10	/* Real Time Clock */
#define INT_SSPINT                      11	/* Synchronous Serial Port */
#define INT_UARTINT0                    12	/* UART 0 on development chip */
#define INT_UARTINT1                    13	/* UART 1 on development chip */
#define INT_UARTINT2                    14	/* UART 2 on development chip */
#define INT_SCIINT                      15	/* Smart Card Interface */
#define INT_CLCDINT                     16	/* CLCD controller */
#define INT_DMAINT                      17	/* DMA controller */
#define INT_PWRFAILINT                  18	/* Power failure */
#define INT_MBXINT                      19	/* Graphics processor */
#define INT_GNDINT                      20	/* Reserved */
	/* External interrupt signals from logic tiles or secondary controller */
#define INT_VICSOURCE21                 21	/* Disk on Chip */
#define INT_VICSOURCE22                 22	/* MCI0A */
#define INT_VICSOURCE23                 23	/* MCI1A */
#define INT_VICSOURCE24                 24	/* AACI */
#define INT_VICSOURCE25                 25	/* Ethernet */
#define INT_VICSOURCE26                 26	/* USB */
#define INT_VICSOURCE27                 27	/* PCI 0 */
#define INT_VICSOURCE28                 28	/* PCI 1 */
#define INT_VICSOURCE29                 29	/* PCI 2 */
#define INT_VICSOURCE30                 30	/* PCI 3 */
#define INT_VICSOURCE31                 31	/* SIC source */

/* 
 *  Interrupt bit positions
 * 
 */
#define INTMASK_WDOGINT                 (1 << INT_WDOGINT)
#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
#define INTMASK_COMMRx                  (1 << INT_COMMRx)
#define INTMASK_COMMTx                  (1 << INT_COMMTx)
#define INTMASK_TIMERINT0_1             (1 << INT_TIMERINT0_1)
#define INTMASK_TIMERINT2_3             (1 << INT_TIMERINT2_3)
#define INTMASK_GPIOINT0                (1 << INT_GPIOINT0)
#define INTMASK_GPIOINT1                (1 << INT_GPIOINT1)
#define INTMASK_GPIOINT2                (1 << INT_GPIOINT2)
#define INTMASK_GPIOINT3                (1 << INT_GPIOINT3)
#define INTMASK_RTCINT                  (1 << INT_RTCINT)
#define INTMASK_SSPINT                  (1 << INT_SSPINT)
#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
#define INTMASK_UARTINT2                (1 << INT_UARTINT2)
#define INTMASK_SCIINT                  (1 << INT_SCIINT)
#define INTMASK_CLCDINT                 (1 << INT_CLCDINT)
#define INTMASK_DMAINT                  (1 << INT_DMAINT)
#define INTMASK_PWRFAILINT              (1 << INT_PWRFAILINT)
#define INTMASK_MBXINT                  (1 << INT_MBXINT)
#define INTMASK_GNDINT                  (1 << INT_GNDINT)
#define INTMASK_VICSOURCE21             (1 << INT_VICSOURCE21)
#define INTMASK_VICSOURCE22             (1 << INT_VICSOURCE22)
#define INTMASK_VICSOURCE23             (1 << INT_VICSOURCE23)
#define INTMASK_VICSOURCE24             (1 << INT_VICSOURCE24)
#define INTMASK_VICSOURCE25             (1 << INT_VICSOURCE25)
#define INTMASK_VICSOURCE26             (1 << INT_VICSOURCE26)
#define INTMASK_VICSOURCE27             (1 << INT_VICSOURCE27)
#define INTMASK_VICSOURCE28             (1 << INT_VICSOURCE28)
#define INTMASK_VICSOURCE29             (1 << INT_VICSOURCE29)
#define INTMASK_VICSOURCE30             (1 << INT_VICSOURCE30)
#define INTMASK_VICSOURCE31             (1 << INT_VICSOURCE31)


#define VERSATILE_SC_VALID_INT               0x003FFFFF

#define MAXIRQNUM                       31
#define MAXFIQNUM                       31
#define MAXSWINUM                       31

/* ------------------------------------------------------------------------
 *  Interrupts - bit assignment (secondary)
 * ------------------------------------------------------------------------
 */
#define SIC_INT_MMCI0B                  1	/* Multimedia Card 0B */
#define SIC_INT_MMCI1B                  2	/* Multimedia Card 1B */
#define SIC_INT_KMI0                    3	/* Keyboard/Mouse port 0 */
#define SIC_INT_KMI1                    4	/* Keyboard/Mouse port 1 */
#define SIC_INT_SCI3                    5	/* Smart Card interface */
#define SIC_INT_UART3                   6	/* UART 3 empty or data available */
#define SIC_INT_CLCD                    7	/* Character LCD */
#define SIC_INT_TOUCH                   8	/* Touchscreen */
#define SIC_INT_KEYPAD                  9	/* Key pressed on display keypad */
	/* 10:20 - reserved */
#define SIC_INT_DoC                     21	/* Disk on Chip memory controller */
#define SIC_INT_MMCI0A                  22	/* MMC 0A */
#define SIC_INT_MMCI1A                  23	/* MMC 1A */
#define SIC_INT_AACI                    24	/* Audio Codec */
#define SIC_INT_ETH                     25	/* Ethernet controller */
#define SIC_INT_USB                     26	/* USB controller */
#define SIC_INT_PCI0                    27
#define SIC_INT_PCI1                    28
#define SIC_INT_PCI2                    29
#define SIC_INT_PCI3                    30


#define SIC_INTMASK_MMCI0B              (1 << SIC_INT_MMCI0B)
#define SIC_INTMASK_MMCI1B              (1 << SIC_INT_MMCI1B)
#define SIC_INTMASK_KMI0                (1 << SIC_INT_KMI0)
#define SIC_INTMASK_KMI1                (1 << SIC_INT_KMI1)
#define SIC_INTMASK_SCI3                (1 << SIC_INT_SCI3)
#define SIC_INTMASK_UART3               (1 << SIC_INT_UART3)
#define SIC_INTMASK_CLCD                (1 << SIC_INT_CLCD)
#define SIC_INTMASK_TOUCH               (1 << SIC_INT_TOUCH)
#define SIC_INTMASK_KEYPAD              (1 << SIC_INT_KEYPAD)
#define SIC_INTMASK_DoC                 (1 << SIC_INT_DoC)
#define SIC_INTMASK_MMCI0A              (1 << SIC_INT_MMCI0A)
#define SIC_INTMASK_MMCI1A              (1 << SIC_INT_MMCI1A)
#define SIC_INTMASK_AACI                (1 << SIC_INT_AACI)
#define SIC_INTMASK_ETH                 (1 << SIC_INT_ETH)
#define SIC_INTMASK_USB                 (1 << SIC_INT_USB)
#define SIC_INTMASK_PCI0                (1 << SIC_INT_PCI0)
#define SIC_INTMASK_PCI1                (1 << SIC_INT_PCI1)
#define SIC_INTMASK_PCI2                (1 << SIC_INT_PCI2)
#define SIC_INTMASK_PCI3                (1 << SIC_INT_PCI3)
/* 
 *  Application Flash
 * 
 */
#define FLASH_BASE                      VERSATILE_FLASH_BASE
#define FLASH_SIZE                      VERSATILE_FLASH_SIZE
#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
#define FLASH_BLOCK_SIZE                SZ_128K

/* 
 *  Boot Flash
 * 
 */
#define EPROM_BASE                      VERSATILE_BOOT_ROM_HI
#define EPROM_SIZE                      VERSATILE_BOOT_ROM_SIZE
#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)

/* 
 *  Clean base - dummy
 * 
 */
#define CLEAN_BASE                      EPROM_BASE

/*
 * System controller bit assignment
 */
#define VERSATILE_REFCLK	0
#define VERSATILE_TIMCLK	1

#define VERSATILE_TIMER1_EnSel	15
#define VERSATILE_TIMER2_EnSel	17
#define VERSATILE_TIMER3_EnSel	19
#define VERSATILE_TIMER4_EnSel	21


#define MAX_TIMER                       2
#define MAX_PERIOD                      699050
#define TICKS_PER_uSEC                  1

/* 
 *  These are useconds NOT ticks.  
 * 
 */
#define mSEC_1                          1000
#define mSEC_5                          (mSEC_1 * 5)
#define mSEC_10                         (mSEC_1 * 10)
#define mSEC_25                         (mSEC_1 * 25)
#define SEC_1                           (mSEC_1 * 1000)

#define VERSATILE_CSR_BASE             0x10000000
#define VERSATILE_CSR_SIZE             0x10000000

#ifdef CONFIG_MACH_VERSATILE_AB
/*
 * IB2 Versatile/AB expansion board definitions
 */
#define VERSATILE_IB2_CAMERA_BANK	VERSATILE_IB2_BASE
#define VERSATILE_IB2_KBD_DATAREG	(VERSATILE_IB2_BASE + 0x01000000)

/* VICINTSOURCE27 */
#define VERSATILE_IB2_INT_BASE		(VERSATILE_IB2_BASE + 0x02000000)
#define VERSATILE_IB2_IER		(VERSATILE_IB2_INT_BASE + 0)
#define VERSATILE_IB2_ISR		(VERSATILE_IB2_INT_BASE + 4)

#define VERSATILE_IB2_CTL_BASE		(VERSATILE_IB2_BASE + 0x03000000)
#define VERSATILE_IB2_CTRL		(VERSATILE_IB2_CTL_BASE + 0)
#define VERSATILE_IB2_STAT		(VERSATILE_IB2_CTL_BASE + 4)
#endif

#endif

/* 	END */