iop331.h

linux-2.6.15.6

/*
 * linux/include/asm/arch-iop3xx/iop331.h
 *
 * Intel IOP331 Chip definitions
 *
 * Author: Dave Jiang ([e-mail])
 * Copyright (C) 2003, 2004 Intel Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _IOP331_HW_H_
#define _IOP331_HW_H_


/*
 * This is needed for mixed drivers that need to work on all
 * IOP3xx variants but behave slightly differently on each.
 */
#ifndef __ASSEMBLY__
#ifdef	CONFIG_ARCH_IOP331
/*#define	iop_is_331()	((processor_id & 0xffffffb0) == 0x69054090) */
#define	iop_is_331()	((processor_id & 0xffffff30) == 0x69054010)
#else
#define	iop_is_331()	0
#endif
#endif

/*
 * IOP331 I/O and Mem space regions for PCI autoconfiguration
 */
#define IOP331_PCI_IO_WINDOW_SIZE   0x00010000
#define IOP331_PCI_LOWER_IO_PA      0x90000000
#define IOP331_PCI_LOWER_IO_VA      0xfe000000
#define IOP331_PCI_LOWER_IO_BA      (*IOP331_OIOWTVR)
#define IOP331_PCI_UPPER_IO_PA      (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_IO_VA      (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_IO_BA      (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_IO_OFFSET        (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)

/* this can be 128M if OMWTVR1 is set */
#define IOP331_PCI_MEM_WINDOW_SIZE	0x04000000 /* 64M outbound window */
/* #define IOP331_PCI_MEM_WINDOW_SIZE  (~*IOP331_IALR1 + 1) */
#define IOP331_PCI_LOWER_MEM_PA     0x80000000
#define IOP331_PCI_LOWER_MEM_BA     (*IOP331_OMWTVR0)
#define IOP331_PCI_UPPER_MEM_PA     (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_MEM_BA     (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_MEM_OFFSET       (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)

/*
 * IOP331 chipset registers
 */
#define IOP331_VIRT_MEM_BASE  0xfeffe000  /* chip virtual mem address*/
#define IOP331_PHYS_MEM_BASE  0xffffe000  /* chip physical memory address */
#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))

/* Reserved 0x00000000 through 0x000000FF */

/* Address Translation Unit 0x00000100 through 0x000001FF */
#define IOP331_ATUVID     (volatile u16 *)IOP331_REG_ADDR(0x00000100)
#define IOP331_ATUDID     (volatile u16 *)IOP331_REG_ADDR(0x00000102)
#define IOP331_ATUCMD     (volatile u16 *)IOP331_REG_ADDR(0x00000104)
#define IOP331_ATUSR      (volatile u16 *)IOP331_REG_ADDR(0x00000106)
#define IOP331_ATURID     (volatile u8  *)IOP331_REG_ADDR(0x00000108)
#define IOP331_ATUCCR     (volatile u32 *)IOP331_REG_ADDR(0x00000109)
#define IOP331_ATUCLSR    (volatile u8  *)IOP331_REG_ADDR(0x0000010C)
#define IOP331_ATULT      (volatile u8  *)IOP331_REG_ADDR(0x0000010D)
#define IOP331_ATUHTR     (volatile u8  *)IOP331_REG_ADDR(0x0000010E)
#define IOP331_ATUBIST    (volatile u8  *)IOP331_REG_ADDR(0x0000010F)
#define IOP331_IABAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000110)
#define IOP331_IAUBAR0    (volatile u32 *)IOP331_REG_ADDR(0x00000114)
#define IOP331_IABAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000118)
#define IOP331_IAUBAR1    (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
#define IOP331_IABAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000120)
#define IOP331_IAUBAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000124)
#define IOP331_ASVIR      (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
#define IOP331_ASIR       (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
#define IOP331_ERBAR      (volatile u32 *)IOP331_REG_ADDR(0x00000130)
#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
/* Reserved 0x00000138 through 0x0000013B */
#define IOP331_ATUILR     (volatile u8  *)IOP331_REG_ADDR(0x0000013C)
#define IOP331_ATUIPR     (volatile u8  *)IOP331_REG_ADDR(0x0000013D)
#define IOP331_ATUMGNT    (volatile u8  *)IOP331_REG_ADDR(0x0000013E)
#define IOP331_ATUMLAT    (volatile u8  *)IOP331_REG_ADDR(0x0000013F)
#define IOP331_IALR0      (volatile u32 *)IOP331_REG_ADDR(0x00000140)
#define IOP331_IATVR0     (volatile u32 *)IOP331_REG_ADDR(0x00000144)
#define IOP331_ERLR       (volatile u32 *)IOP331_REG_ADDR(0x00000148)
#define IOP331_ERTVR      (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
#define IOP331_IALR1      (volatile u32 *)IOP331_REG_ADDR(0x00000150)
#define IOP331_IALR2      (volatile u32 *)IOP331_REG_ADDR(0x00000154)
#define IOP331_IATVR2     (volatile u32 *)IOP331_REG_ADDR(0x00000158)
#define IOP331_OIOWTVR    (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
#define IOP331_OMWTVR0    (volatile u32 *)IOP331_REG_ADDR(0x00000160)
#define IOP331_OUMWTVR0   (volatile u32 *)IOP331_REG_ADDR(0x00000164)
#define IOP331_OMWTVR1    (volatile u32 *)IOP331_REG_ADDR(0x00000168)
#define IOP331_OUMWTVR1   (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
/* Reserved 0x00000170 through 0x00000177*/
#define IOP331_OUDWTVR    (volatile u32 *)IOP331_REG_ADDR(0x00000178)
/* Reserved 0x0000017C through 0x0000017F*/
#define IOP331_ATUCR      (volatile u32 *)IOP331_REG_ADDR(0x00000180)
#define IOP331_PCSR       (volatile u32 *)IOP331_REG_ADDR(0x00000184)
#define IOP331_ATUISR     (volatile u32 *)IOP331_REG_ADDR(0x00000188)
#define IOP331_ATUIMR     (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
#define IOP331_IABAR3     (volatile u32 *)IOP331_REG_ADDR(0x00000190)
#define IOP331_IAUBAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000194)
#define IOP331_IALR3      (volatile u32 *)IOP331_REG_ADDR(0x00000198)
#define IOP331_IATVR3     (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
/* Reserved 0x000001A0 through 0x000001A3*/
#define IOP331_OCCAR      (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
/* Reserved 0x000001A8 through 0x000001AB*/
#define IOP331_OCCDR      (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
/* Reserved 0x000001B0 through 0x000001BB*/
#define IOP331_VPDCAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
#define IOP331_VPDNXTP    (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
#define IOP331_VPDAR	  (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
#define IOP331_VPDDR      (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
#define IOP331_PMCAPID    (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
#define IOP331_PMNEXT     (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
#define IOP331_APMCR      (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
#define IOP331_APMCSR     (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
/* Reserved 0x000001C6 through 0x000001CF */
#define IOP331_MSICAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
#define IOP331_MSINXTP	  (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
#define IOP331_MSIMCR     (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
#define IOP331_MSIMAR     (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
#define IOP331_MSIMUAR	  (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
#define IOP331_MSIMDR	  (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
#define IOP331_PCIXCAPID  (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
#define IOP331_PCIXNEXT   (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
#define IOP331_PCIXCMD    (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
#define IOP331_PCIXSR     (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
#define IOP331_PCIIRSR    (volatile u32 *)IOP331_REG_ADDR(0x000001EC)

/* Messaging Unit 0x00000300 through 0x000003FF */

/* Reserved 0x00000300 through 0x0000030c */
#define IOP331_IMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000310)
#define IOP331_IMR1       (volatile u32 *)IOP331_REG_ADDR(0x00000314)
#define IOP331_OMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000318)
#define IOP331_OMR1       (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
#define IOP331_IDR        (volatile u32 *)IOP331_REG_ADDR(0x00000320)
#define IOP331_IISR       (volatile u32 *)IOP331_REG_ADDR(0x00000324)
#define IOP331_IIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000328)
#define IOP331_ODR        (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
#define IOP331_OISR       (volatile u32 *)IOP331_REG_ADDR(0x00000330)
#define IOP331_OIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000334)
/* Reserved 0x00000338 through 0x0000034F */
#define IOP331_MUCR       (volatile u32 *)IOP331_REG_ADDR(0x00000350)
#define IOP331_QBAR       (volatile u32 *)IOP331_REG_ADDR(0x00000354)
/* Reserved 0x00000358 through 0x0000035C */
#define IOP331_IFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000360)
#define IOP331_IFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000364)
#define IOP331_IPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000368)
#define IOP331_IPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
#define IOP331_OFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000370)
#define IOP331_OFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000374)
#define IOP331_OPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000378)
#define IOP331_OPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
#define IOP331_IAR        (volatile u32 *)IOP331_REG_ADDR(0x00000380)
/* Reserved 0x00000384 through 0x000003FF */

/* DMA Controller 0x00000400 through 0x000004FF */
#define IOP331_DMA0_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000400)
#define IOP331_DMA0_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000404)
#define IOP331_DMA0_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
#define IOP331_DMA0_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000410)
#define IOP331_DMA0_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000414)
#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
#define IOP331_DMA0_LADR  (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
#define IOP331_DMA0_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000420)
#define IOP331_DMA0_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000424)
/* Reserved 0x00000428 through 0x0000043C */
#define IOP331_DMA1_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000440)
#define IOP331_DMA1_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000444)
#define IOP331_DMA1_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
#define IOP331_DMA1_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000450)
#define IOP331_DMA1_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000454)
#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
#define IOP331_DMA1_LADR  (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
#define IOP331_DMA1_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000460)