bif_dma_defs_asm.h

linux-2.6.15.6

#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch3_ctrl_offset 96

/* Register rw_ch3_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
#define reg_bif_dma_rw_ch3_addr___addr___width 32
#define reg_bif_dma_rw_ch3_addr_offset 100

/* Register rw_ch3_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_start___run___lsb 0
#define reg_bif_dma_rw_ch3_start___run___width 1
#define reg_bif_dma_rw_ch3_start___run___bit 0
#define reg_bif_dma_rw_ch3_start_offset 104

/* Register rw_ch3_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch3_cnt_offset 108

/* Register r_ch3_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
#define reg_bif_dma_r_ch3_stat___cnt___width 16
#define reg_bif_dma_r_ch3_stat___run___lsb 31
#define reg_bif_dma_r_ch3_stat___run___width 1
#define reg_bif_dma_r_ch3_stat___run___bit 31
#define reg_bif_dma_r_ch3_stat_offset 112

/* Register rw_intr_mask, scope bif_dma, type rw */
#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
#define reg_bif_dma_rw_intr_mask_offset 128

/* Register rw_ack_intr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
#define reg_bif_dma_rw_ack_intr_offset 132

/* Register r_intr, scope bif_dma, type r */
#define reg_bif_dma_r_intr___ext_dma0___lsb 0
#define reg_bif_dma_r_intr___ext_dma0___width 1
#define reg_bif_dma_r_intr___ext_dma0___bit 0
#define reg_bif_dma_r_intr___ext_dma1___lsb 1
#define reg_bif_dma_r_intr___ext_dma1___width 1
#define reg_bif_dma_r_intr___ext_dma1___bit 1
#define reg_bif_dma_r_intr___ext_dma2___lsb 2
#define reg_bif_dma_r_intr___ext_dma2___width 1
#define reg_bif_dma_r_intr___ext_dma2___bit 2
#define reg_bif_dma_r_intr___ext_dma3___lsb 3
#define reg_bif_dma_r_intr___ext_dma3___width 1
#define reg_bif_dma_r_intr___ext_dma3___bit 3
#define reg_bif_dma_r_intr_offset 136

/* Register r_masked_intr, scope bif_dma, type r */
#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
#define reg_bif_dma_r_masked_intr_offset 140

/* Register rw_pin0_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin0_cfg_offset 160

/* Register rw_pin1_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin1_cfg_offset 164

/* Register rw_pin2_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin2_cfg_offset 168

/* Register rw_pin3_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin3_cfg_offset 172

/* Register rw_pin4_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin4_cfg_offset 176

/* Register rw_pin5_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin5_cfg_offset 180

/* Register rw_pin6_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin6_cfg_offset 184

/* Register rw_pin7_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin7_cfg_offset 188

/* Register r_pin_stat, scope bif_dma, type r */
#define reg_bif_dma_r_pin_stat___pin0___lsb 0
#define reg_bif_dma_r_pin_stat___pin0___width 1
#define reg_bif_dma_r_pin_stat___pin0___bit 0
#define reg_bif_dma_r_pin_stat___pin1___lsb 1
#define reg_bif_dma_r_pin_stat___pin1___width 1
#define reg_bif_dma_r_pin_stat___pin1___bit 1
#define reg_bif_dma_r_pin_stat___pin2___lsb 2
#define reg_bif_dma_r_pin_stat___pin2___width 1
#define reg_bif_dma_r_pin_stat___pin2___bit 2
#define reg_bif_dma_r_pin_stat___pin3___lsb 3
#define reg_bif_dma_r_pin_stat___pin3___width 1
#define reg_bif_dma_r_pin_stat___pin3___bit 3
#define reg_bif_dma_r_pin_stat___pin4___lsb 4
#define reg_bif_dma_r_pin_stat___pin4___width 1
#define reg_bif_dma_r_pin_stat___pin4___bit 4
#define reg_bif_dma_r_pin_stat___pin5___lsb 5
#define reg_bif_dma_r_pin_stat___pin5___width 1
#define reg_bif_dma_r_pin_stat___pin5___bit 5
#define reg_bif_dma_r_pin_stat___pin6___lsb 6
#define reg_bif_dma_r_pin_stat___pin6___width 1
#define reg_bif_dma_r_pin_stat___pin6___bit 6
#define reg_bif_dma_r_pin_stat___pin7___lsb 7
#define reg_bif_dma_r_pin_stat___pin7___width 1
#define reg_bif_dma_r_pin_stat___pin7___bit 7
#define reg_bif_dma_r_pin_stat_offset 192


/* Constants */
#define regk_bif_dma_as_master                    0x00000001
#define regk_bif_dma_as_slave                     0x00000001
#define regk_bif_dma_burst1                       0x00000000
#define regk_bif_dma_burst8                       0x00000001
#define regk_bif_dma_bw16                         0x00000001
#define regk_bif_dma_bw32                         0x00000002
#define regk_bif_dma_bw8                          0x00000000
#define regk_bif_dma_dack                         0x00000006
#define regk_bif_dma_dack_inv                     0x00000007
#define regk_bif_dma_force                        0x00000001
#define regk_bif_dma_hi                           0x00000003
#define regk_bif_dma_inv                          0x00000003
#define regk_bif_dma_lo                           0x00000002
#define regk_bif_dma_master                       0x00000001
#define regk_bif_dma_no                           0x00000000
#define regk_bif_dma_norm                         0x00000002
#define regk_bif_dma_off                          0x00000000
#define regk_bif_dma_rw_ch0_ctrl_default          0x00000000
#define regk_bif_dma_rw_ch0_start_default         0x00000000
#define regk_bif_dma_rw_ch1_ctrl_default          0x00000000
#define regk_bif_dma_rw_ch1_start_default         0x00000000
#define regk_bif_dma_rw_ch2_ctrl_default          0x00000000
#define regk_bif_dma_rw_ch2_start_default         0x00000000
#define regk_bif_dma_rw_ch3_ctrl_default          0x00000000
#define regk_bif_dma_rw_ch3_start_default         0x00000000
#define regk_bif_dma_rw_intr_mask_default         0x00000000
#define regk_bif_dma_rw_pin0_cfg_default          0x00000000
#define regk_bif_dma_rw_pin1_cfg_default          0x00000000
#define regk_bif_dma_rw_pin2_cfg_default          0x00000000
#define regk_bif_dma_rw_pin3_cfg_default          0x00000000
#define regk_bif_dma_rw_pin4_cfg_default          0x00000000
#define regk_bif_dma_rw_pin5_cfg_default          0x00000000
#define regk_bif_dma_rw_pin6_cfg_default          0x00000000
#define regk_bif_dma_rw_pin7_cfg_default          0x00000000
#define regk_bif_dma_slave                        0x00000002
#define regk_bif_dma_sreq                         0x00000006
#define regk_bif_dma_sreq_inv                     0x00000007
#define regk_bif_dma_tc                           0x00000004
#define regk_bif_dma_tc_inv                       0x00000005
#define regk_bif_dma_yes                          0x00000001
#endif /* __bif_dma_defs_asm_h */