bif_dma_defs_asm.h

linux-2.6.15.6

#ifndef __bif_dma_defs_asm_h
#define __bif_dma_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/bif/rtl/bif_dma_regs.r
 *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
 *     last modfied: Mon Apr 11 16:06:33 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
 *      id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

/* Register rw_ch0_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
#define reg_bif_dma_rw_ch0_ctrl_offset 0

/* Register rw_ch0_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
#define reg_bif_dma_rw_ch0_addr___addr___width 32
#define reg_bif_dma_rw_ch0_addr_offset 4

/* Register rw_ch0_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_start___run___lsb 0
#define reg_bif_dma_rw_ch0_start___run___width 1
#define reg_bif_dma_rw_ch0_start___run___bit 0
#define reg_bif_dma_rw_ch0_start_offset 8

/* Register rw_ch0_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch0_cnt_offset 12

/* Register r_ch0_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
#define reg_bif_dma_r_ch0_stat___cnt___width 16
#define reg_bif_dma_r_ch0_stat___run___lsb 31
#define reg_bif_dma_r_ch0_stat___run___width 1
#define reg_bif_dma_r_ch0_stat___run___bit 31
#define reg_bif_dma_r_ch0_stat_offset 16

/* Register rw_ch1_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch1_ctrl_offset 32

/* Register rw_ch1_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
#define reg_bif_dma_rw_ch1_addr___addr___width 32
#define reg_bif_dma_rw_ch1_addr_offset 36

/* Register rw_ch1_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_start___run___lsb 0
#define reg_bif_dma_rw_ch1_start___run___width 1
#define reg_bif_dma_rw_ch1_start___run___bit 0
#define reg_bif_dma_rw_ch1_start_offset 40

/* Register rw_ch1_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch1_cnt_offset 44

/* Register r_ch1_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
#define reg_bif_dma_r_ch1_stat___cnt___width 16
#define reg_bif_dma_r_ch1_stat___run___lsb 31
#define reg_bif_dma_r_ch1_stat___run___width 1
#define reg_bif_dma_r_ch1_stat___run___bit 31
#define reg_bif_dma_r_ch1_stat_offset 48

/* Register rw_ch2_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
#define reg_bif_dma_rw_ch2_ctrl_offset 64

/* Register rw_ch2_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
#define reg_bif_dma_rw_ch2_addr___addr___width 32
#define reg_bif_dma_rw_ch2_addr_offset 68

/* Register rw_ch2_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_start___run___lsb 0
#define reg_bif_dma_rw_ch2_start___run___width 1
#define reg_bif_dma_rw_ch2_start___run___bit 0
#define reg_bif_dma_rw_ch2_start_offset 72

/* Register rw_ch2_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch2_cnt_offset 76

/* Register r_ch2_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
#define reg_bif_dma_r_ch2_stat___cnt___width 16
#define reg_bif_dma_r_ch2_stat___run___lsb 31
#define reg_bif_dma_r_ch2_stat___run___width 1
#define reg_bif_dma_r_ch2_stat___run___bit 31
#define reg_bif_dma_r_ch2_stat_offset 80

/* Register rw_ch3_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2