eth_defs_asm.h

linux-2.6.15.6

#define reg_eth_rs_tr_cnt___late_col___width 8
#define reg_eth_rs_tr_cnt___deferred___lsb 24
#define reg_eth_rs_tr_cnt___deferred___width 8
#define reg_eth_rs_tr_cnt_offset 56

/* Register r_tr_cnt, scope eth, type r */
#define reg_eth_r_tr_cnt___single_col___lsb 0
#define reg_eth_r_tr_cnt___single_col___width 8
#define reg_eth_r_tr_cnt___mult_col___lsb 8
#define reg_eth_r_tr_cnt___mult_col___width 8
#define reg_eth_r_tr_cnt___late_col___lsb 16
#define reg_eth_r_tr_cnt___late_col___width 8
#define reg_eth_r_tr_cnt___deferred___lsb 24
#define reg_eth_r_tr_cnt___deferred___width 8
#define reg_eth_r_tr_cnt_offset 60

/* Register rs_phy_cnt, scope eth, type rs */
#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
#define reg_eth_rs_phy_cnt___carrier_loss___width 8
#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
#define reg_eth_rs_phy_cnt___sqe_err___width 8
#define reg_eth_rs_phy_cnt_offset 64

/* Register r_phy_cnt, scope eth, type r */
#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
#define reg_eth_r_phy_cnt___carrier_loss___width 8
#define reg_eth_r_phy_cnt___sqe_err___lsb 8
#define reg_eth_r_phy_cnt___sqe_err___width 8
#define reg_eth_r_phy_cnt_offset 68

/* Register rw_test_ctrl, scope eth, type rw */
#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
#define reg_eth_rw_test_ctrl___snmp_inc___width 1
#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
#define reg_eth_rw_test_ctrl___snmp___lsb 1
#define reg_eth_rw_test_ctrl___snmp___width 1
#define reg_eth_rw_test_ctrl___snmp___bit 1
#define reg_eth_rw_test_ctrl___backoff___lsb 2
#define reg_eth_rw_test_ctrl___backoff___width 1
#define reg_eth_rw_test_ctrl___backoff___bit 2
#define reg_eth_rw_test_ctrl_offset 72

/* Register rw_intr_mask, scope eth, type rw */
#define reg_eth_rw_intr_mask___crc___lsb 0
#define reg_eth_rw_intr_mask___crc___width 1
#define reg_eth_rw_intr_mask___crc___bit 0
#define reg_eth_rw_intr_mask___align___lsb 1
#define reg_eth_rw_intr_mask___align___width 1
#define reg_eth_rw_intr_mask___align___bit 1
#define reg_eth_rw_intr_mask___oversize___lsb 2
#define reg_eth_rw_intr_mask___oversize___width 1
#define reg_eth_rw_intr_mask___oversize___bit 2
#define reg_eth_rw_intr_mask___congestion___lsb 3
#define reg_eth_rw_intr_mask___congestion___width 1
#define reg_eth_rw_intr_mask___congestion___bit 3
#define reg_eth_rw_intr_mask___single_col___lsb 4
#define reg_eth_rw_intr_mask___single_col___width 1
#define reg_eth_rw_intr_mask___single_col___bit 4
#define reg_eth_rw_intr_mask___mult_col___lsb 5
#define reg_eth_rw_intr_mask___mult_col___width 1
#define reg_eth_rw_intr_mask___mult_col___bit 5
#define reg_eth_rw_intr_mask___late_col___lsb 6
#define reg_eth_rw_intr_mask___late_col___width 1
#define reg_eth_rw_intr_mask___late_col___bit 6
#define reg_eth_rw_intr_mask___deferred___lsb 7
#define reg_eth_rw_intr_mask___deferred___width 1
#define reg_eth_rw_intr_mask___deferred___bit 7
#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
#define reg_eth_rw_intr_mask___carrier_loss___width 1
#define reg_eth_rw_intr_mask___carrier_loss___bit 8
#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
#define reg_eth_rw_intr_mask___sqe_test_err___width 1
#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
#define reg_eth_rw_intr_mask___orun___lsb 10
#define reg_eth_rw_intr_mask___orun___width 1
#define reg_eth_rw_intr_mask___orun___bit 10
#define reg_eth_rw_intr_mask___urun___lsb 11
#define reg_eth_rw_intr_mask___urun___width 1
#define reg_eth_rw_intr_mask___urun___bit 11
#define reg_eth_rw_intr_mask___excessive_col___lsb 12
#define reg_eth_rw_intr_mask___excessive_col___width 1
#define reg_eth_rw_intr_mask___excessive_col___bit 12
#define reg_eth_rw_intr_mask___mdio___lsb 13
#define reg_eth_rw_intr_mask___mdio___width 1
#define reg_eth_rw_intr_mask___mdio___bit 13
#define reg_eth_rw_intr_mask_offset 76

/* Register rw_ack_intr, scope eth, type rw */
#define reg_eth_rw_ack_intr___crc___lsb 0
#define reg_eth_rw_ack_intr___crc___width 1
#define reg_eth_rw_ack_intr___crc___bit 0
#define reg_eth_rw_ack_intr___align___lsb 1
#define reg_eth_rw_ack_intr___align___width 1
#define reg_eth_rw_ack_intr___align___bit 1
#define reg_eth_rw_ack_intr___oversize___lsb 2
#define reg_eth_rw_ack_intr___oversize___width 1
#define reg_eth_rw_ack_intr___oversize___bit 2
#define reg_eth_rw_ack_intr___congestion___lsb 3
#define reg_eth_rw_ack_intr___congestion___width 1
#define reg_eth_rw_ack_intr___congestion___bit 3
#define reg_eth_rw_ack_intr___single_col___lsb 4
#define reg_eth_rw_ack_intr___single_col___width 1
#define reg_eth_rw_ack_intr___single_col___bit 4
#define reg_eth_rw_ack_intr___mult_col___lsb 5
#define reg_eth_rw_ack_intr___mult_col___width 1
#define reg_eth_rw_ack_intr___mult_col___bit 5
#define reg_eth_rw_ack_intr___late_col___lsb 6
#define reg_eth_rw_ack_intr___late_col___width 1
#define reg_eth_rw_ack_intr___late_col___bit 6
#define reg_eth_rw_ack_intr___deferred___lsb 7
#define reg_eth_rw_ack_intr___deferred___width 1
#define reg_eth_rw_ack_intr___deferred___bit 7
#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
#define reg_eth_rw_ack_intr___carrier_loss___width 1
#define reg_eth_rw_ack_intr___carrier_loss___bit 8
#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
#define reg_eth_rw_ack_intr___sqe_test_err___width 1
#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
#define reg_eth_rw_ack_intr___orun___lsb 10
#define reg_eth_rw_ack_intr___orun___width 1
#define reg_eth_rw_ack_intr___orun___bit 10
#define reg_eth_rw_ack_intr___urun___lsb 11
#define reg_eth_rw_ack_intr___urun___width 1
#define reg_eth_rw_ack_intr___urun___bit 11
#define reg_eth_rw_ack_intr___excessive_col___lsb 12
#define reg_eth_rw_ack_intr___excessive_col___width 1
#define reg_eth_rw_ack_intr___excessive_col___bit 12
#define reg_eth_rw_ack_intr___mdio___lsb 13
#define reg_eth_rw_ack_intr___mdio___width 1
#define reg_eth_rw_ack_intr___mdio___bit 13
#define reg_eth_rw_ack_intr_offset 80

/* Register r_intr, scope eth, type r */
#define reg_eth_r_intr___crc___lsb 0
#define reg_eth_r_intr___crc___width 1
#define reg_eth_r_intr___crc___bit 0
#define reg_eth_r_intr___align___lsb 1
#define reg_eth_r_intr___align___width 1
#define reg_eth_r_intr___align___bit 1
#define reg_eth_r_intr___oversize___lsb 2
#define reg_eth_r_intr___oversize___width 1
#define reg_eth_r_intr___oversize___bit 2
#define reg_eth_r_intr___congestion___lsb 3
#define reg_eth_r_intr___congestion___width 1
#define reg_eth_r_intr___congestion___bit 3
#define reg_eth_r_intr___single_col___lsb 4
#define reg_eth_r_intr___single_col___width 1
#define reg_eth_r_intr___single_col___bit 4
#define reg_eth_r_intr___mult_col___lsb 5
#define reg_eth_r_intr___mult_col___width 1
#define reg_eth_r_intr___mult_col___bit 5
#define reg_eth_r_intr___late_col___lsb 6
#define reg_eth_r_intr___late_col___width 1
#define reg_eth_r_intr___late_col___bit 6
#define reg_eth_r_intr___deferred___lsb 7
#define reg_eth_r_intr___deferred___width 1
#define reg_eth_r_intr___deferred___bit 7
#define reg_eth_r_intr___carrier_loss___lsb 8
#define reg_eth_r_intr___carrier_loss___width 1
#define reg_eth_r_intr___carrier_loss___bit 8
#define reg_eth_r_intr___sqe_test_err___lsb 9
#define reg_eth_r_intr___sqe_test_err___width 1
#define reg_eth_r_intr___sqe_test_err___bit 9
#define reg_eth_r_intr___orun___lsb 10
#define reg_eth_r_intr___orun___width 1
#define reg_eth_r_intr___orun___bit 10
#define reg_eth_r_intr___urun___lsb 11
#define reg_eth_r_intr___urun___width 1
#define reg_eth_r_intr___urun___bit 11
#define reg_eth_r_intr___excessive_col___lsb 12
#define reg_eth_r_intr___excessive_col___width 1
#define reg_eth_r_intr___excessive_col___bit 12
#define reg_eth_r_intr___mdio___lsb 13
#define reg_eth_r_intr___mdio___width 1
#define reg_eth_r_intr___mdio___bit 13
#define reg_eth_r_intr_offset 84

/* Register r_masked_intr, scope eth, type r */
#define reg_eth_r_masked_intr___crc___lsb 0
#define reg_eth_r_masked_intr___crc___width 1
#define reg_eth_r_masked_intr___crc___bit 0
#define reg_eth_r_masked_intr___align___lsb 1
#define reg_eth_r_masked_intr___align___width 1
#define reg_eth_r_masked_intr___align___bit 1
#define reg_eth_r_masked_intr___oversize___lsb 2
#define reg_eth_r_masked_intr___oversize___width 1
#define reg_eth_r_masked_intr___oversize___bit 2
#define reg_eth_r_masked_intr___congestion___lsb 3
#define reg_eth_r_masked_intr___congestion___width 1
#define reg_eth_r_masked_intr___congestion___bit 3
#define reg_eth_r_masked_intr___single_col___lsb 4
#define reg_eth_r_masked_intr___single_col___width 1
#define reg_eth_r_masked_intr___single_col___bit 4
#define reg_eth_r_masked_intr___mult_col___lsb 5
#define reg_eth_r_masked_intr___mult_col___width 1
#define reg_eth_r_masked_intr___mult_col___bit 5
#define reg_eth_r_masked_intr___late_col___lsb 6
#define reg_eth_r_masked_intr___late_col___width 1
#define reg_eth_r_masked_intr___late_col___bit 6
#define reg_eth_r_masked_intr___deferred___lsb 7
#define reg_eth_r_masked_intr___deferred___width 1
#define reg_eth_r_masked_intr___deferred___bit 7
#define reg_eth_r_masked_intr___carrier_loss___lsb 8
#define reg_eth_r_masked_intr___carrier_loss___width 1
#define reg_eth_r_masked_intr___carrier_loss___bit 8
#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
#define reg_eth_r_masked_intr___sqe_test_err___width 1
#define reg_eth_r_masked_intr___sqe_test_err___bit 9
#define reg_eth_r_masked_intr___orun___lsb 10
#define reg_eth_r_masked_intr___orun___width 1
#define reg_eth_r_masked_intr___orun___bit 10
#define reg_eth_r_masked_intr___urun___lsb 11
#define reg_eth_r_masked_intr___urun___width 1
#define reg_eth_r_masked_intr___urun___bit 11
#define reg_eth_r_masked_intr___excessive_col___lsb 12
#define reg_eth_r_masked_intr___excessive_col___width 1
#define reg_eth_r_masked_intr___excessive_col___bit 12
#define reg_eth_r_masked_intr___mdio___lsb 13
#define reg_eth_r_masked_intr___mdio___width 1
#define reg_eth_r_masked_intr___mdio___bit 13
#define reg_eth_r_masked_intr_offset 88


/* Constants */
#define regk_eth_discard                          0x00000000
#define regk_eth_ether                            0x00000000
#define regk_eth_full                             0x00000001
#define regk_eth_half                             0x00000000
#define regk_eth_hsh                              0x00000001
#define regk_eth_mii                              0x00000001
#define regk_eth_mii_clk                          0x00000000
#define regk_eth_mii_rec                          0x00000002
#define regk_eth_no                               0x00000000
#define regk_eth_rec                              0x00000001
#define regk_eth_rw_ga_hi_default                 0x00000000
#define regk_eth_rw_ga_lo_default                 0x00000000
#define regk_eth_rw_gen_ctrl_default              0x00000000
#define regk_eth_rw_intr_mask_default             0x00000000
#define regk_eth_rw_ma0_hi_default                0x00000000
#define regk_eth_rw_ma0_lo_default                0x00000000
#define regk_eth_rw_ma1_hi_default                0x00000000
#define regk_eth_rw_ma1_lo_default                0x00000000
#define regk_eth_rw_mgm_ctrl_default              0x00000000
#define regk_eth_rw_test_ctrl_default             0x00000000
#define regk_eth_size1518                         0x00000000
#define regk_eth_size1522                         0x00000001
#define regk_eth_yes                              0x00000001
#endif /* __eth_defs_asm_h */