📄 iop_sw_mpu_defs.h
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unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr2 : 1; unsigned int spu1_intr2 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr3 : 1; unsigned int spu1_intr3 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_r_masked_intr_grp0;#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */typedef struct { unsigned int spu0_intr4 : 1; unsigned int spu1_intr4 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr5 : 1; unsigned int spu1_intr5 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr6 : 1; unsigned int spu1_intr6 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr7 : 1; unsigned int spu1_intr7 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_rw_intr_grp1_mask;#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */typedef struct { unsigned int spu0_intr4 : 1; unsigned int spu1_intr4 : 1; unsigned int dummy1 : 6; unsigned int spu0_intr5 : 1; unsigned int spu1_intr5 : 1; unsigned int dummy2 : 6; unsigned int spu0_intr6 : 1; unsigned int spu1_intr6 : 1; unsigned int dummy3 : 6; unsigned int spu0_intr7 : 1; unsigned int spu1_intr7 : 1; unsigned int dummy4 : 6;} reg_iop_sw_mpu_rw_ack_intr_grp1;#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116/* Register r_intr_grp1, scope iop_sw_mpu, type r */typedef struct { unsigned int spu0_intr4 : 1; unsigned int spu1_intr4 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr5 : 1; unsigned int spu1_intr5 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr6 : 1; unsigned int spu1_intr6 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr7 : 1; unsigned int spu1_intr7 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_r_intr_grp1;#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */typedef struct { unsigned int spu0_intr4 : 1; unsigned int spu1_intr4 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr5 : 1; unsigned int spu1_intr5 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr6 : 1; unsigned int spu1_intr6 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr7 : 1; unsigned int spu1_intr7 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_r_masked_intr_grp1;#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */typedef struct { unsigned int spu0_intr8 : 1; unsigned int spu1_intr8 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr9 : 1; unsigned int spu1_intr9 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr10 : 1; unsigned int spu1_intr10 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr11 : 1; unsigned int spu1_intr11 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_rw_intr_grp2_mask;#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */typedef struct { unsigned int spu0_intr8 : 1; unsigned int spu1_intr8 : 1; unsigned int dummy1 : 6; unsigned int spu0_intr9 : 1; unsigned int spu1_intr9 : 1; unsigned int dummy2 : 6; unsigned int spu0_intr10 : 1; unsigned int spu1_intr10 : 1; unsigned int dummy3 : 6; unsigned int spu0_intr11 : 1; unsigned int spu1_intr11 : 1; unsigned int dummy4 : 6;} reg_iop_sw_mpu_rw_ack_intr_grp2;#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132/* Register r_intr_grp2, scope iop_sw_mpu, type r */typedef struct { unsigned int spu0_intr8 : 1; unsigned int spu1_intr8 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr9 : 1; unsigned int spu1_intr9 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr10 : 1; unsigned int spu1_intr10 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr11 : 1; unsigned int spu1_intr11 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_r_intr_grp2;#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */typedef struct { unsigned int spu0_intr8 : 1; unsigned int spu1_intr8 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr9 : 1; unsigned int spu1_intr9 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr10 : 1; unsigned int spu1_intr10 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr11 : 1; unsigned int spu1_intr11 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_r_masked_intr_grp2;#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */typedef struct { unsigned int spu0_intr12 : 1; unsigned int spu1_intr12 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr13 : 1; unsigned int spu1_intr13 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr14 : 1; unsigned int spu1_intr14 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr15 : 1; unsigned int spu1_intr15 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_rw_intr_grp3_mask;#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */typedef struct { unsigned int spu0_intr12 : 1; unsigned int spu1_intr12 : 1; unsigned int dummy1 : 6; unsigned int spu0_intr13 : 1; unsigned int spu1_intr13 : 1; unsigned int dummy2 : 6; unsigned int spu0_intr14 : 1; unsigned int spu1_intr14 : 1; unsigned int dummy3 : 6; unsigned int spu0_intr15 : 1; unsigned int spu1_intr15 : 1; unsigned int dummy4 : 6;} reg_iop_sw_mpu_rw_ack_intr_grp3;#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148/* Register r_intr_grp3, scope iop_sw_mpu, type r */typedef struct { unsigned int spu0_intr12 : 1; unsigned int spu1_intr12 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr13 : 1; unsigned int spu1_intr13 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr14 : 1; unsigned int spu1_intr14 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr15 : 1; unsigned int spu1_intr15 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_r_intr_grp3;#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */typedef struct { unsigned int spu0_intr12 : 1; unsigned int spu1_intr12 : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_out0 : 1; unsigned int spu0_intr13 : 1; unsigned int spu1_intr13 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp4 : 1; unsigned int timer_grp1 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out0_extra : 1; unsigned int dmc_in0 : 1; unsigned int spu0_intr14 : 1; unsigned int spu1_intr14 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp5 : 1; unsigned int timer_grp2 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int dmc_out1 : 1; unsigned int spu0_intr15 : 1; unsigned int spu1_intr15 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp6 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int dmc_in1 : 1;} reg_iop_sw_mpu_r_masked_intr_grp3;#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156/* Constants */enum { regk_iop_sw_mpu_copy = 0x00000000, regk_iop_sw_mpu_cpu = 0x00000000, regk_iop_sw_mpu_mpu = 0x00000001, regk_iop_sw_mpu_no = 0x00000000, regk_iop_sw_mpu_nop = 0x00000000, regk_iop_sw_mpu_rd = 0x00000002, regk_iop_sw_mpu_reg_copy = 0x00000001, regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, regk_iop_sw_mpu_set = 0x00000001, regk_iop_sw_mpu_spu0 = 0x00000002, regk_iop_sw_mpu_spu1 = 0x00000003, regk_iop_sw_mpu_wr = 0x00000003, regk_iop_sw_mpu_yes = 0x00000001};#endif /* __iop_sw_mpu_defs_h */⌨️ 快捷键说明
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