📄 iop_spu_defs.h
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typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in;#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124/* Register r_stat_in, scope iop_spu, type r */typedef struct { unsigned int timer_grp_lo : 4; unsigned int fifo_out_last : 1; unsigned int fifo_out_rdy : 1; unsigned int fifo_out_all : 1; unsigned int fifo_in_rdy : 1; unsigned int dmc_out_all : 1; unsigned int dmc_out_dth : 1; unsigned int dmc_out_eop : 1; unsigned int dmc_out_dv : 1; unsigned int dmc_out_last : 1; unsigned int dmc_out_cmd_rq : 1; unsigned int dmc_out_cmd_rdy : 1; unsigned int pcrc_correct : 1; unsigned int timer_grp_hi : 4; unsigned int dmc_in_sth : 1; unsigned int dmc_in_full : 1; unsigned int dmc_in_cmd_rdy : 1; unsigned int spu_gio_out : 4; unsigned int sync_clk12 : 1; unsigned int scrc_out_data : 1; unsigned int scrc_in_err : 1; unsigned int mc_busy : 1; unsigned int mc_owned : 1;} reg_iop_spu_r_stat_in;#define REG_RD_ADDR_iop_spu_r_stat_in 128/* Register r_trigger_in, scope iop_spu, type r */typedef unsigned int reg_iop_spu_r_trigger_in;#define REG_RD_ADDR_iop_spu_r_trigger_in 132/* Register r_special_stat, scope iop_spu, type r */typedef struct { unsigned int c_flag : 1; unsigned int v_flag : 1; unsigned int z_flag : 1; unsigned int n_flag : 1; unsigned int xor_bus0_r2_0 : 1; unsigned int xor_bus1_r3_0 : 1; unsigned int xor_bus0m_r2_0 : 1; unsigned int xor_bus1m_r3_0 : 1; unsigned int fsm_in0 : 1; unsigned int fsm_in1 : 1; unsigned int fsm_in2 : 1; unsigned int fsm_in3 : 1; unsigned int fsm_in4 : 1; unsigned int fsm_in5 : 1; unsigned int fsm_in6 : 1; unsigned int fsm_in7 : 1; unsigned int event0 : 1; unsigned int event1 : 1; unsigned int event2 : 1; unsigned int event3 : 1; unsigned int dummy1 : 12;} reg_iop_spu_r_special_stat;#define REG_RD_ADDR_iop_spu_r_special_stat 136/* Register rw_reg_access, scope iop_spu, type rw */typedef struct { unsigned int addr : 13; unsigned int dummy1 : 3; unsigned int imm_hi : 16;} reg_iop_spu_rw_reg_access;#define REG_RD_ADDR_iop_spu_rw_reg_access 140#define REG_WR_ADDR_iop_spu_rw_reg_access 140#define STRIDE_iop_spu_rw_event_cfg 4/* Register rw_event_cfg, scope iop_spu, type rw */typedef struct { unsigned int addr : 12; unsigned int src : 2; unsigned int eq_en : 1; unsigned int eq_inv : 1; unsigned int gt_en : 1; unsigned int gt_inv : 1; unsigned int dummy1 : 14;} reg_iop_spu_rw_event_cfg;#define REG_RD_ADDR_iop_spu_rw_event_cfg 144#define REG_WR_ADDR_iop_spu_rw_event_cfg 144#define STRIDE_iop_spu_rw_event_mask 4/* Register rw_event_mask, scope iop_spu, type rw */typedef unsigned int reg_iop_spu_rw_event_mask;#define REG_RD_ADDR_iop_spu_rw_event_mask 160#define REG_WR_ADDR_iop_spu_rw_event_mask 160#define STRIDE_iop_spu_rw_event_val 4/* Register rw_event_val, scope iop_spu, type rw */typedef unsigned int reg_iop_spu_rw_event_val;#define REG_RD_ADDR_iop_spu_rw_event_val 176#define REG_WR_ADDR_iop_spu_rw_event_val 176/* Register rw_event_ret, scope iop_spu, type rw */typedef struct { unsigned int addr : 12; unsigned int dummy1 : 20;} reg_iop_spu_rw_event_ret;#define REG_RD_ADDR_iop_spu_rw_event_ret 192#define REG_WR_ADDR_iop_spu_rw_event_ret 192/* Register r_trace, scope iop_spu, type r */typedef struct { unsigned int fsm : 1; unsigned int en : 1; unsigned int c_flag : 1; unsigned int v_flag : 1; unsigned int z_flag : 1; unsigned int n_flag : 1; unsigned int seq_addr : 12; unsigned int dummy1 : 2; unsigned int fsm_addr : 12;} reg_iop_spu_r_trace;#define REG_RD_ADDR_iop_spu_r_trace 196/* Register r_fsm_trace, scope iop_spu, type r */typedef struct { unsigned int fsm : 1; unsigned int en : 1; unsigned int tmr_done : 1; unsigned int inp0 : 1; unsigned int inp1 : 1; unsigned int inp2 : 1; unsigned int inp3 : 1; unsigned int event0 : 1; unsigned int event1 : 1; unsigned int event2 : 1; unsigned int event3 : 1; unsigned int gio_out : 8; unsigned int dummy1 : 1; unsigned int fsm_addr : 12;} reg_iop_spu_r_fsm_trace;#define REG_RD_ADDR_iop_spu_r_fsm_trace 200#define STRIDE_iop_spu_rw_brp 4/* Register rw_brp, scope iop_spu, type rw */typedef struct { unsigned int addr : 12; unsigned int fsm : 1; unsigned int en : 1; unsigned int dummy1 : 18;} reg_iop_spu_rw_brp;#define REG_RD_ADDR_iop_spu_rw_brp 204#define REG_WR_ADDR_iop_spu_rw_brp 204/* Constants */enum { regk_iop_spu_attn_hi = 0x00000005, regk_iop_spu_attn_lo = 0x00000005, regk_iop_spu_attn_r0 = 0x00000000, regk_iop_spu_attn_r1 = 0x00000001, regk_iop_spu_attn_r10 = 0x00000002, regk_iop_spu_attn_r11 = 0x00000003, regk_iop_spu_attn_r12 = 0x00000004, regk_iop_spu_attn_r13 = 0x00000005, regk_iop_spu_attn_r14 = 0x00000006, regk_iop_spu_attn_r15 = 0x00000007, regk_iop_spu_attn_r2 = 0x00000002, regk_iop_spu_attn_r3 = 0x00000003, regk_iop_spu_attn_r4 = 0x00000004, regk_iop_spu_attn_r5 = 0x00000005, regk_iop_spu_attn_r6 = 0x00000006, regk_iop_spu_attn_r7 = 0x00000007, regk_iop_spu_attn_r8 = 0x00000000, regk_iop_spu_attn_r9 = 0x00000001, regk_iop_spu_c = 0x00000000, regk_iop_spu_flag = 0x00000002, regk_iop_spu_gio_in = 0x00000000, regk_iop_spu_gio_out = 0x00000005, regk_iop_spu_gio_out0 = 0x00000008, regk_iop_spu_gio_out1 = 0x00000009, regk_iop_spu_gio_out2 = 0x0000000a, regk_iop_spu_gio_out3 = 0x0000000b, regk_iop_spu_gio_out4 = 0x0000000c, regk_iop_spu_gio_out5 = 0x0000000d, regk_iop_spu_gio_out6 = 0x0000000e, regk_iop_spu_gio_out7 = 0x0000000f, regk_iop_spu_n = 0x00000003, regk_iop_spu_no = 0x00000000, regk_iop_spu_r0 = 0x00000008, regk_iop_spu_r1 = 0x00000009, regk_iop_spu_r10 = 0x0000000a, regk_iop_spu_r11 = 0x0000000b, regk_iop_spu_r12 = 0x0000000c, regk_iop_spu_r13 = 0x0000000d, regk_iop_spu_r14 = 0x0000000e, regk_iop_spu_r15 = 0x0000000f, regk_iop_spu_r2 = 0x0000000a, regk_iop_spu_r3 = 0x0000000b, regk_iop_spu_r4 = 0x0000000c, regk_iop_spu_r5 = 0x0000000d, regk_iop_spu_r6 = 0x0000000e, regk_iop_spu_r7 = 0x0000000f, regk_iop_spu_r8 = 0x00000008, regk_iop_spu_r9 = 0x00000009, regk_iop_spu_reg_hi = 0x00000002, regk_iop_spu_reg_lo = 0x00000002, regk_iop_spu_rw_brp_default = 0x00000000, regk_iop_spu_rw_brp_size = 0x00000004, regk_iop_spu_rw_ctrl_default = 0x00000000, regk_iop_spu_rw_event_cfg_size = 0x00000004, regk_iop_spu_rw_event_mask_size = 0x00000004, regk_iop_spu_rw_event_val_size = 0x00000004, regk_iop_spu_rw_gio_out_default = 0x00000000, regk_iop_spu_rw_r_size = 0x00000010, regk_iop_spu_rw_reg_access_default = 0x00000000, regk_iop_spu_stat_in = 0x00000002, regk_iop_spu_statin_hi = 0x00000004, regk_iop_spu_statin_lo = 0x00000004, regk_iop_spu_trig = 0x00000003, regk_iop_spu_trigger = 0x00000006, regk_iop_spu_v = 0x00000001, regk_iop_spu_wsts_gioout_spec = 0x00000001, regk_iop_spu_xor = 0x00000003, regk_iop_spu_xor_bus0_r2_0 = 0x00000000, regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, regk_iop_spu_xor_bus1_r3_0 = 0x00000001, regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, regk_iop_spu_yes = 0x00000001, regk_iop_spu_z = 0x00000002};#endif /* __iop_spu_defs_h */⌨️ 快捷键说明
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