iop_spu_defs.h

linux-2.6.15.6

#ifndef __iop_spu_defs_h
#define __iop_spu_defs_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/iop_spu.r
 *     id:           <not found>
 *     last modfied: Mon Apr 11 16:08:46 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
 *      id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope iop_spu */

#define STRIDE_iop_spu_rw_r 4
/* Register rw_r, scope iop_spu, type rw */
typedef unsigned int reg_iop_spu_rw_r;
#define REG_RD_ADDR_iop_spu_rw_r 0
#define REG_WR_ADDR_iop_spu_rw_r 0

/* Register rw_seq_pc, scope iop_spu, type rw */
typedef struct {
  unsigned int addr : 12;
  unsigned int dummy1 : 20;
} reg_iop_spu_rw_seq_pc;
#define REG_RD_ADDR_iop_spu_rw_seq_pc 64
#define REG_WR_ADDR_iop_spu_rw_seq_pc 64

/* Register rw_fsm_pc, scope iop_spu, type rw */
typedef struct {
  unsigned int addr : 12;
  unsigned int dummy1 : 20;
} reg_iop_spu_rw_fsm_pc;
#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68

/* Register rw_ctrl, scope iop_spu, type rw */
typedef struct {
  unsigned int fsm : 1;
  unsigned int en  : 1;
  unsigned int dummy1 : 30;
} reg_iop_spu_rw_ctrl;
#define REG_RD_ADDR_iop_spu_rw_ctrl 72
#define REG_WR_ADDR_iop_spu_rw_ctrl 72

/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
typedef struct {
  unsigned int val0 : 5;
  unsigned int src0 : 3;
  unsigned int val1 : 5;
  unsigned int src1 : 3;
  unsigned int val2 : 5;
  unsigned int src2 : 3;
  unsigned int val3 : 5;
  unsigned int src3 : 3;
} reg_iop_spu_rw_fsm_inputs3_0;
#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76

/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
typedef struct {
  unsigned int val4 : 5;
  unsigned int src4 : 3;
  unsigned int val5 : 5;
  unsigned int src5 : 3;
  unsigned int val6 : 5;
  unsigned int src6 : 3;
  unsigned int val7 : 5;
  unsigned int src7 : 3;
} reg_iop_spu_rw_fsm_inputs7_4;
#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80

/* Register rw_gio_out, scope iop_spu, type rw */
typedef unsigned int reg_iop_spu_rw_gio_out;
#define REG_RD_ADDR_iop_spu_rw_gio_out 84
#define REG_WR_ADDR_iop_spu_rw_gio_out 84

/* Register rw_bus0_out, scope iop_spu, type rw */
typedef unsigned int reg_iop_spu_rw_bus0_out;
#define REG_RD_ADDR_iop_spu_rw_bus0_out 88
#define REG_WR_ADDR_iop_spu_rw_bus0_out 88

/* Register rw_bus1_out, scope iop_spu, type rw */
typedef unsigned int reg_iop_spu_rw_bus1_out;
#define REG_RD_ADDR_iop_spu_rw_bus1_out 92
#define REG_WR_ADDR_iop_spu_rw_bus1_out 92

/* Register r_gio_in, scope iop_spu, type r */
typedef unsigned int reg_iop_spu_r_gio_in;
#define REG_RD_ADDR_iop_spu_r_gio_in 96

/* Register r_bus0_in, scope iop_spu, type r */
typedef unsigned int reg_iop_spu_r_bus0_in;
#define REG_RD_ADDR_iop_spu_r_bus0_in 100

/* Register r_bus1_in, scope iop_spu, type r */
typedef unsigned int reg_iop_spu_r_bus1_in;
#define REG_RD_ADDR_iop_spu_r_bus1_in 104

/* Register rw_gio_out_set, scope iop_spu, type rw */
typedef unsigned int reg_iop_spu_rw_gio_out_set;
#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108

/* Register rw_gio_out_clr, scope iop_spu, type rw */
typedef unsigned int reg_iop_spu_rw_gio_out_clr;
#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112

/* Register rs_wr_stat, scope iop_spu, type rs */
typedef struct {
  unsigned int r0  : 1;
  unsigned int r1  : 1;
  unsigned int r2  : 1;
  unsigned int r3  : 1;
  unsigned int r4  : 1;
  unsigned int r5  : 1;
  unsigned int r6  : 1;
  unsigned int r7  : 1;
  unsigned int r8  : 1;
  unsigned int r9  : 1;
  unsigned int r10 : 1;
  unsigned int r11 : 1;
  unsigned int r12 : 1;
  unsigned int r13 : 1;
  unsigned int r14 : 1;
  unsigned int r15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_spu_rs_wr_stat;
#define REG_RD_ADDR_iop_spu_rs_wr_stat 116

/* Register r_wr_stat, scope iop_spu, type r */
typedef struct {
  unsigned int r0  : 1;
  unsigned int r1  : 1;
  unsigned int r2  : 1;
  unsigned int r3  : 1;
  unsigned int r4  : 1;
  unsigned int r5  : 1;
  unsigned int r6  : 1;
  unsigned int r7  : 1;
  unsigned int r8  : 1;
  unsigned int r9  : 1;
  unsigned int r10 : 1;
  unsigned int r11 : 1;
  unsigned int r12 : 1;
  unsigned int r13 : 1;
  unsigned int r14 : 1;
  unsigned int r15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_spu_r_wr_stat;
#define REG_RD_ADDR_iop_spu_r_wr_stat 120

/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */