📄 iop_sw_cfg_defs.h
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unsigned int in_last : 2; unsigned int in_strb : 4; unsigned int out_src : 1; unsigned int dummy1 : 13;} reg_iop_sw_cfg_rw_pdp1_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int sdp_out0_strb : 3; unsigned int sdp_out1_strb : 3; unsigned int sdp_in0_data : 3; unsigned int sdp_in0_last : 2; unsigned int sdp_in0_strb : 3; unsigned int sdp_in1_data : 3; unsigned int sdp_in1_last : 2; unsigned int sdp_in1_strb : 3; unsigned int dummy1 : 10;} reg_iop_sw_cfg_rw_sdp_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236/* Constants */enum { regk_iop_sw_cfg_a = 0x00000001, regk_iop_sw_cfg_b = 0x00000002, regk_iop_sw_cfg_bus0 = 0x00000000, regk_iop_sw_cfg_bus0_rot16 = 0x00000004, regk_iop_sw_cfg_bus0_rot24 = 0x00000006, regk_iop_sw_cfg_bus0_rot8 = 0x00000002, regk_iop_sw_cfg_bus1 = 0x00000001, regk_iop_sw_cfg_bus1_rot16 = 0x00000005, regk_iop_sw_cfg_bus1_rot24 = 0x00000007, regk_iop_sw_cfg_bus1_rot8 = 0x00000003, regk_iop_sw_cfg_clk12 = 0x00000000, regk_iop_sw_cfg_cpu = 0x00000000, regk_iop_sw_cfg_dmc0 = 0x00000000, regk_iop_sw_cfg_dmc1 = 0x00000001, regk_iop_sw_cfg_gated_clk0 = 0x00000010, regk_iop_sw_cfg_gated_clk1 = 0x00000011, regk_iop_sw_cfg_gated_clk2 = 0x00000012, regk_iop_sw_cfg_gated_clk3 = 0x00000013, regk_iop_sw_cfg_gio0 = 0x00000004, regk_iop_sw_cfg_gio1 = 0x00000001, regk_iop_sw_cfg_gio2 = 0x00000005, regk_iop_sw_cfg_gio3 = 0x00000002, regk_iop_sw_cfg_gio4 = 0x00000006, regk_iop_sw_cfg_gio5 = 0x00000003, regk_iop_sw_cfg_gio6 = 0x00000007, regk_iop_sw_cfg_gio7 = 0x00000004, regk_iop_sw_cfg_gio_in0 = 0x00000000, regk_iop_sw_cfg_gio_in1 = 0x00000001, regk_iop_sw_cfg_gio_in10 = 0x00000002, regk_iop_sw_cfg_gio_in11 = 0x00000003, regk_iop_sw_cfg_gio_in14 = 0x00000004, regk_iop_sw_cfg_gio_in15 = 0x00000005, regk_iop_sw_cfg_gio_in18 = 0x00000002, regk_iop_sw_cfg_gio_in19 = 0x00000003, regk_iop_sw_cfg_gio_in20 = 0x00000004, regk_iop_sw_cfg_gio_in21 = 0x00000005, regk_iop_sw_cfg_gio_in26 = 0x00000006, regk_iop_sw_cfg_gio_in27 = 0x00000007, regk_iop_sw_cfg_gio_in28 = 0x00000006, regk_iop_sw_cfg_gio_in29 = 0x00000007, regk_iop_sw_cfg_gio_in4 = 0x00000000, regk_iop_sw_cfg_gio_in5 = 0x00000001, regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, regk_iop_sw_cfg_mpu = 0x00000001, regk_iop_sw_cfg_none = 0x00000000, regk_iop_sw_cfg_par0 = 0x00000000, regk_iop_sw_cfg_par1 = 0x00000001, regk_iop_sw_cfg_pdp_out0 = 0x00000002, regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, regk_iop_sw_cfg_pdp_out1 = 0x00000003, regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, regk_iop_sw_cfg_sdp_out0 = 0x00000008, regk_iop_sw_cfg_sdp_out1 = 0x00000009, regk_iop_sw_cfg_size16 = 0x00000002, regk_iop_sw_cfg_size24 = 0x00000003, regk_iop_sw_cfg_size32 = 0x00000004, regk_iop_sw_cfg_size8 = 0x00000001, regk_iop_sw_cfg_spu0 = 0x00000002, regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, regk_iop_sw_cfg_spu0_g0 = 0x0000000e, regk_iop_sw_cfg_spu0_g1 = 0x0000000e, regk_iop_sw_cfg_spu0_g2 = 0x0000000e, regk_iop_sw_cfg_spu0_g3 = 0x0000000e, regk_iop_sw_cfg_spu0_g4 = 0x0000000e, regk_iop_sw_cfg_spu0_g5 = 0x0000000e, regk_iop_sw_cfg_spu0_g6 = 0x0000000e, regk_iop_sw_cfg_spu0_g7 = 0x0000000e, regk_iop_sw_cfg_spu0_gio0 = 0x00000000, regk_iop_sw_cfg_spu0_gio1 = 0x00000001, regk_iop_sw_cfg_spu0_gio2 = 0x00000000, regk_iop_sw_cfg_spu0_gio5 = 0x00000005, regk_iop_sw_cfg_spu0_gio6 = 0x00000006, regk_iop_sw_cfg_spu0_gio7 = 0x00000007, regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, regk_iop_sw_cfg_spu1 = 0x00000003, regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, regk_iop_sw_cfg_spu1_g0 = 0x0000000f, regk_iop_sw_cfg_spu1_g1 = 0x0000000f, regk_iop_sw_cfg_spu1_g2 = 0x0000000f, regk_iop_sw_cfg_spu1_g3 = 0x0000000f, regk_iop_sw_cfg_spu1_g4 = 0x0000000f, regk_iop_sw_cfg_spu1_g5 = 0x0000000f, regk_iop_sw_cfg_spu1_g6 = 0x0000000f, regk_iop_sw_cfg_spu1_g7 = 0x0000000f, regk_iop_sw_cfg_spu1_gio0 = 0x00000002, regk_iop_sw_cfg_spu1_gio1 = 0x00000003, regk_iop_sw_cfg_spu1_gio2 = 0x00000002, regk_iop_sw_cfg_spu1_gio5 = 0x00000005, regk_iop_sw_cfg_spu1_gio6 = 0x00000006, regk_iop_sw_cfg_spu1_gio7 = 0x00000007, regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, regk_iop_sw_cfg_timer_grp0 = 0x00000000, regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, regk_iop_sw_cfg_timer_grp1 = 0x00000000, regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, regk_iop_sw_cfg_timer_grp2 = 0x00000000, regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, regk_iop_sw_cfg_timer_grp3 = 0x00000000, regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, regk_iop_sw_cfg_trig0_0 = 0x00000000, regk_iop_sw_cfg_trig0_1 = 0x00000000, regk_iop_sw_cfg_trig0_2 = 0x00000000, regk_iop_sw_cfg_trig0_3 = 0x00000000, regk_iop_sw_cfg_trig1_0 = 0x00000000, regk_iop_sw_cfg_trig1_1 = 0x00000000, regk_iop_sw_cfg_trig1_2 = 0x00000000, regk_iop_sw_cfg_trig1_3 = 0x00000000, regk_iop_sw_cfg_trig2_0 = 0x00000000, regk_iop_sw_cfg_trig2_1 = 0x00000000, regk_iop_sw_cfg_trig2_2 = 0x00000000, regk_iop_sw_cfg_trig2_3 = 0x00000000, regk_iop_sw_cfg_trig3_0 = 0x00000000, regk_iop_sw_cfg_trig3_1 = 0x00000000, regk_iop_sw_cfg_trig3_2 = 0x00000000, regk_iop_sw_cfg_trig3_3 = 0x00000000, regk_iop_sw_cfg_trig4_0 = 0x00000001, regk_iop_sw_cfg_trig4_1 = 0x00000001, regk_iop_sw_cfg_trig4_2 = 0x00000001, regk_iop_sw_cfg_trig4_3 = 0x00000001, regk_iop_sw_cfg_trig5_0 = 0x00000001, regk_iop_sw_cfg_trig5_1 = 0x00000001, regk_iop_sw_cfg_trig5_2 = 0x00000001, regk_iop_sw_cfg_trig5_3 = 0x00000001, regk_iop_sw_cfg_trig6_0 = 0x00000001, regk_iop_sw_cfg_trig6_1 = 0x00000001, regk_iop_sw_cfg_trig6_2 = 0x00000001, regk_iop_sw_cfg_trig6_3 = 0x00000001, regk_iop_sw_cfg_trig7_0 = 0x00000001, regk_iop_sw_cfg_trig7_1 = 0x00000001, regk_iop_sw_cfg_trig7_2 = 0x00000001, regk_iop_sw_cfg_trig7_3 = 0x00000001};#endif /* __iop_sw_cfg_defs_h */⌨️ 快捷键说明
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