iop_sw_cfg_defs.h

linux-2.6.15.6

#ifndef __iop_sw_cfg_defs_h
#define __iop_sw_cfg_defs_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
 *     id:           <not found>
 *     last modfied: Mon Apr 11 16:10:19 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
 *      id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope iop_sw_cfg */

/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_crc_par0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0

/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_crc_par1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4

/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_in0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8

/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_in1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12

/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_out0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16

/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_dmc_out1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20

/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24

/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28

/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32

/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36

/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40

/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44

/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48

/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52

/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_sap_in_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56

/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_sap_out_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60

/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_in0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64

/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_in1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68

/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_out0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72

/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_scrc_out1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76

/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_spu0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80

/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_spu1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84

/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88

/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92

/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp2_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96

/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_timer_grp3_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100

/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp0_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104

/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp1_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108

/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp2_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112

/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp3_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116

/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp4_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120

/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp5_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124

/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
typedef struct {
  unsigned int cfg : 2;
  unsigned int dummy1 : 30;
} reg_iop_sw_cfg_rw_trigger_grp6_owner;
#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128