iop_sw_cpu_defs_asm.h

linux-2.6.15.6

#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
#define reg_iop_sw_cpu_rw_ack_intr1_offset 104

/* Register r_intr1, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
#define reg_iop_sw_cpu_r_intr1_offset 108

/* Register r_masked_intr1, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24