iop_sw_cpu_defs_asm.h

linux-2.6.15.6

#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
#define reg_iop_sw_cpu_rw_intr0_mask_offset 84

/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
#define reg_iop_sw_cpu_rw_ack_intr0_offset 88

/* Register r_intr0, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1