iop_sw_mpu_defs_asm.h

linux-2.6.15.6

#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108

/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112

/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116

/* Register r_intr_grp1, scope iop_sw_mpu, type r */
#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10