iop_sw_cfg_defs_asm.h

linux-2.6.15.6

#define regk_iop_sw_cfg_pdp_out1_hi_rot8          0x00000005
#define regk_iop_sw_cfg_pdp_out1_lo               0x00000002
#define regk_iop_sw_cfg_pdp_out1_lo_rot8          0x00000004
#define regk_iop_sw_cfg_rw_bus0_mask_default      0x00000000
#define regk_iop_sw_cfg_rw_bus0_oe_mask_default   0x00000000
#define regk_iop_sw_cfg_rw_bus1_mask_default      0x00000000
#define regk_iop_sw_cfg_rw_bus1_oe_mask_default   0x00000000
#define regk_iop_sw_cfg_rw_bus_out_cfg_default    0x00000000
#define regk_iop_sw_cfg_rw_crc_par0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_crc_par1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_dmc_in0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_dmc_in1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_dmc_out0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_dmc_out1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_in0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_in1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_out0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_fifo_out1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_mask_default       0x00000000
#define regk_iop_sw_cfg_rw_gio_oe_mask_default    0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_pdp0_cfg_default       0x00000000
#define regk_iop_sw_cfg_rw_pdp1_cfg_default       0x00000000
#define regk_iop_sw_cfg_rw_pinmapping_default     0x55555555
#define regk_iop_sw_cfg_rw_sap_in_owner_default   0x00000000
#define regk_iop_sw_cfg_rw_sap_out_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_scrc_in0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_scrc_in1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_scrc_out0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_scrc_out1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_sdp_cfg_default        0x00000000
#define regk_iop_sw_cfg_rw_spu0_cfg_default       0x00000000
#define regk_iop_sw_cfg_rw_spu0_owner_default     0x00000000
#define regk_iop_sw_cfg_rw_spu1_cfg_default       0x00000000
#define regk_iop_sw_cfg_rw_spu1_owner_default     0x00000000
#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp2_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default  0x00000000
#define regk_iop_sw_cfg_rw_timer_grp3_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default  0x00000000
#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default  0x00000000
#define regk_iop_sw_cfg_sdp_out0                  0x00000008
#define regk_iop_sw_cfg_sdp_out1                  0x00000009
#define regk_iop_sw_cfg_size16                    0x00000002
#define regk_iop_sw_cfg_size24                    0x00000003
#define regk_iop_sw_cfg_size32                    0x00000004
#define regk_iop_sw_cfg_size8                     0x00000001
#define regk_iop_sw_cfg_spu0                      0x00000002
#define regk_iop_sw_cfg_spu0_bus_out0_hi          0x00000006
#define regk_iop_sw_cfg_spu0_bus_out0_lo          0x00000006
#define regk_iop_sw_cfg_spu0_bus_out1_hi          0x00000007
#define regk_iop_sw_cfg_spu0_bus_out1_lo          0x00000007
#define regk_iop_sw_cfg_spu0_g0                   0x0000000e
#define regk_iop_sw_cfg_spu0_g1                   0x0000000e
#define regk_iop_sw_cfg_spu0_g2                   0x0000000e
#define regk_iop_sw_cfg_spu0_g3                   0x0000000e
#define regk_iop_sw_cfg_spu0_g4                   0x0000000e
#define regk_iop_sw_cfg_spu0_g5                   0x0000000e
#define regk_iop_sw_cfg_spu0_g6                   0x0000000e
#define regk_iop_sw_cfg_spu0_g7                   0x0000000e
#define regk_iop_sw_cfg_spu0_gio0                 0x00000000
#define regk_iop_sw_cfg_spu0_gio1                 0x00000001
#define regk_iop_sw_cfg_spu0_gio2                 0x00000000
#define regk_iop_sw_cfg_spu0_gio5                 0x00000005
#define regk_iop_sw_cfg_spu0_gio6                 0x00000006
#define regk_iop_sw_cfg_spu0_gio7                 0x00000007
#define regk_iop_sw_cfg_spu0_gio_out0             0x00000008
#define regk_iop_sw_cfg_spu0_gio_out1             0x00000009
#define regk_iop_sw_cfg_spu0_gio_out2             0x0000000a
#define regk_iop_sw_cfg_spu0_gio_out3             0x0000000b
#define regk_iop_sw_cfg_spu0_gio_out4             0x0000000c
#define regk_iop_sw_cfg_spu0_gio_out5             0x0000000d
#define regk_iop_sw_cfg_spu0_gio_out6             0x0000000e
#define regk_iop_sw_cfg_spu0_gio_out7             0x0000000f
#define regk_iop_sw_cfg_spu0_gioout0              0x00000000
#define regk_iop_sw_cfg_spu0_gioout1              0x00000000
#define regk_iop_sw_cfg_spu0_gioout10             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout11             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout12             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout13             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout14             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout15             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout16             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout17             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout18             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout19             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout2              0x00000002
#define regk_iop_sw_cfg_spu0_gioout20             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout21             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout22             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout23             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout24             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout25             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout26             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout27             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout28             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout29             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout3              0x00000002
#define regk_iop_sw_cfg_spu0_gioout30             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout31             0x0000000e
#define regk_iop_sw_cfg_spu0_gioout4              0x00000004
#define regk_iop_sw_cfg_spu0_gioout5              0x00000004
#define regk_iop_sw_cfg_spu0_gioout6              0x00000006
#define regk_iop_sw_cfg_spu0_gioout7              0x00000006
#define regk_iop_sw_cfg_spu0_gioout8              0x0000000e
#define regk_iop_sw_cfg_spu0_gioout9              0x0000000e
#define regk_iop_sw_cfg_spu1                      0x00000003
#define regk_iop_sw_cfg_spu1_bus_out0_hi          0x00000006
#define regk_iop_sw_cfg_spu1_bus_out0_lo          0x00000006
#define regk_iop_sw_cfg_spu1_bus_out1_hi          0x00000007
#define regk_iop_sw_cfg_spu1_bus_out1_lo          0x00000007
#define regk_iop_sw_cfg_spu1_g0                   0x0000000f
#define regk_iop_sw_cfg_spu1_g1                   0x0000000f
#define regk_iop_sw_cfg_spu1_g2                   0x0000000f
#define regk_iop_sw_cfg_spu1_g3                   0x0000000f
#define regk_iop_sw_cfg_spu1_g4                   0x0000000f
#define regk_iop_sw_cfg_spu1_g5                   0x0000000f
#define regk_iop_sw_cfg_spu1_g6                   0x0000000f
#define regk_iop_sw_cfg_spu1_g7                   0x0000000f
#define regk_iop_sw_cfg_spu1_gio0                 0x00000002
#define regk_iop_sw_cfg_spu1_gio1                 0x00000003
#define regk_iop_sw_cfg_spu1_gio2                 0x00000002
#define regk_iop_sw_cfg_spu1_gio5                 0x00000005
#define regk_iop_sw_cfg_spu1_gio6                 0x00000006
#define regk_iop_sw_cfg_spu1_gio7                 0x00000007
#define regk_iop_sw_cfg_spu1_gio_out0             0x00000008
#define regk_iop_sw_cfg_spu1_gio_out1             0x00000009
#define regk_iop_sw_cfg_spu1_gio_out2             0x0000000a
#define regk_iop_sw_cfg_spu1_gio_out3             0x0000000b
#define regk_iop_sw_cfg_spu1_gio_out4             0x0000000c
#define regk_iop_sw_cfg_spu1_gio_out5             0x0000000d
#define regk_iop_sw_cfg_spu1_gio_out6             0x0000000e
#define regk_iop_sw_cfg_spu1_gio_out7             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout0              0x00000001
#define regk_iop_sw_cfg_spu1_gioout1              0x00000001
#define regk_iop_sw_cfg_spu1_gioout10             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout11             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout12             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout13             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout14             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout15             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout16             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout17             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout18             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout19             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout2              0x00000003
#define regk_iop_sw_cfg_spu1_gioout20             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout21             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout22             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout23             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout24             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout25             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout26             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout27             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout28             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout29             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout3              0x00000003
#define regk_iop_sw_cfg_spu1_gioout30             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout31             0x0000000f
#define regk_iop_sw_cfg_spu1_gioout4              0x00000005
#define regk_iop_sw_cfg_spu1_gioout5              0x00000005
#define regk_iop_sw_cfg_spu1_gioout6              0x00000007
#define regk_iop_sw_cfg_spu1_gioout7              0x00000007
#define regk_iop_sw_cfg_spu1_gioout8              0x0000000f
#define regk_iop_sw_cfg_spu1_gioout9              0x0000000f
#define regk_iop_sw_cfg_strb_timer_grp0_tmr0      0x00000001
#define regk_iop_sw_cfg_strb_timer_grp0_tmr1      0x00000002
#define regk_iop_sw_cfg_strb_timer_grp1_tmr0      0x00000001
#define regk_iop_sw_cfg_strb_timer_grp1_tmr1      0x00000002
#define regk_iop_sw_cfg_strb_timer_grp2_tmr0      0x00000003
#define regk_iop_sw_cfg_strb_timer_grp2_tmr1      0x00000002
#define regk_iop_sw_cfg_strb_timer_grp3_tmr0      0x00000003
#define regk_iop_sw_cfg_strb_timer_grp3_tmr1      0x00000002
#define regk_iop_sw_cfg_timer_grp0                0x00000000
#define regk_iop_sw_cfg_timer_grp0_rot            0x00000001
#define regk_iop_sw_cfg_timer_grp0_strb0          0x0000000a
#define regk_iop_sw_cfg_timer_grp0_strb1          0x0000000a
#define regk_iop_sw_cfg_timer_grp0_strb2          0x0000000a
#define regk_iop_sw_cfg_timer_grp0_strb3          0x0000000a
#define regk_iop_sw_cfg_timer_grp0_tmr0           0x00000004
#define regk_iop_sw_cfg_timer_grp0_tmr1           0x00000004
#define regk_iop_sw_cfg_timer_grp1                0x00000000
#define regk_iop_sw_cfg_timer_grp1_rot            0x00000001
#define regk_iop_sw_cfg_timer_grp1_strb0          0x0000000b
#define regk_iop_sw_cfg_timer_grp1_strb1          0x0000000b
#define regk_iop_sw_cfg_timer_grp1_strb2          0x0000000b
#define regk_iop_sw_cfg_timer_grp1_strb3          0x0000000b
#define regk_iop_sw_cfg_timer_grp1_tmr0           0x00000005
#define regk_iop_sw_cfg_timer_grp1_tmr1           0x00000005
#define regk_iop_sw_cfg_timer_grp2                0x00000000
#define regk_iop_sw_cfg_timer_grp2_rot            0x00000001
#define regk_iop_sw_cfg_timer_grp2_strb0          0x0000000c
#define regk_iop_sw_cfg_timer_grp2_strb1          0x0000000c
#define regk_iop_sw_cfg_timer_grp2_strb2          0x0000000c
#define regk_iop_sw_cfg_timer_grp2_strb3          0x0000000c
#define regk_iop_sw_cfg_timer_grp2_tmr0           0x00000006
#define regk_iop_sw_cfg_timer_grp2_tmr1           0x00000006
#define regk_iop_sw_cfg_timer_grp3                0x00000000
#define regk_iop_sw_cfg_timer_grp3_rot            0x00000001
#define regk_iop_sw_cfg_timer_grp3_strb0          0x0000000d
#define regk_iop_sw_cfg_timer_grp3_strb1          0x0000000d
#define regk_iop_sw_cfg_timer_grp3_strb2          0x0000000d
#define regk_iop_sw_cfg_timer_grp3_strb3          0x0000000d
#define regk_iop_sw_cfg_timer_grp3_tmr0           0x00000007
#define regk_iop_sw_cfg_timer_grp3_tmr1           0x00000007
#define regk_iop_sw_cfg_trig0_0                   0x00000000
#define regk_iop_sw_cfg_trig0_1                   0x00000000
#define regk_iop_sw_cfg_trig0_2                   0x00000000
#define regk_iop_sw_cfg_trig0_3                   0x00000000
#define regk_iop_sw_cfg_trig1_0                   0x00000000
#define regk_iop_sw_cfg_trig1_1                   0x00000000
#define regk_iop_sw_cfg_trig1_2                   0x00000000
#define regk_iop_sw_cfg_trig1_3                   0x00000000
#define regk_iop_sw_cfg_trig2_0                   0x00000000
#define regk_iop_sw_cfg_trig2_1                   0x00000000
#define regk_iop_sw_cfg_trig2_2                   0x00000000
#define regk_iop_sw_cfg_trig2_3                   0x00000000
#define regk_iop_sw_cfg_trig3_0                   0x00000000
#define regk_iop_sw_cfg_trig3_1                   0x00000000
#define regk_iop_sw_cfg_trig3_2                   0x00000000
#define regk_iop_sw_cfg_trig3_3                   0x00000000
#define regk_iop_sw_cfg_trig4_0                   0x00000001
#define regk_iop_sw_cfg_trig4_1                   0x00000001
#define regk_iop_sw_cfg_trig4_2                   0x00000001
#define regk_iop_sw_cfg_trig4_3                   0x00000001
#define regk_iop_sw_cfg_trig5_0                   0x00000001
#define regk_iop_sw_cfg_trig5_1                   0x00000001
#define regk_iop_sw_cfg_trig5_2                   0x00000001
#define regk_iop_sw_cfg_trig5_3                   0x00000001
#define regk_iop_sw_cfg_trig6_0                   0x00000001
#define regk_iop_sw_cfg_trig6_1                   0x00000001
#define regk_iop_sw_cfg_trig6_2                   0x00000001
#define regk_iop_sw_cfg_trig6_3                   0x00000001
#define regk_iop_sw_cfg_trig7_0                   0x00000001
#define regk_iop_sw_cfg_trig7_1                   0x00000001
#define regk_iop_sw_cfg_trig7_2                   0x00000001
#define regk_iop_sw_cfg_trig7_3                   0x00000001
#endif /* __iop_sw_cfg_defs_asm_h */