iop_sw_cfg_defs_asm.h

linux-2.6.15.6

#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208

/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212

/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216

/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220

/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224

/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228

/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232

/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236


/* Constants */
#define regk_iop_sw_cfg_a                         0x00000001
#define regk_iop_sw_cfg_b                         0x00000002
#define regk_iop_sw_cfg_bus0                      0x00000000
#define regk_iop_sw_cfg_bus0_rot16                0x00000004
#define regk_iop_sw_cfg_bus0_rot24                0x00000006
#define regk_iop_sw_cfg_bus0_rot8                 0x00000002
#define regk_iop_sw_cfg_bus1                      0x00000001
#define regk_iop_sw_cfg_bus1_rot16                0x00000005
#define regk_iop_sw_cfg_bus1_rot24                0x00000007
#define regk_iop_sw_cfg_bus1_rot8                 0x00000003
#define regk_iop_sw_cfg_clk12                     0x00000000
#define regk_iop_sw_cfg_cpu                       0x00000000
#define regk_iop_sw_cfg_dmc0                      0x00000000
#define regk_iop_sw_cfg_dmc1                      0x00000001
#define regk_iop_sw_cfg_gated_clk0                0x00000010
#define regk_iop_sw_cfg_gated_clk1                0x00000011
#define regk_iop_sw_cfg_gated_clk2                0x00000012
#define regk_iop_sw_cfg_gated_clk3                0x00000013
#define regk_iop_sw_cfg_gio0                      0x00000004
#define regk_iop_sw_cfg_gio1                      0x00000001
#define regk_iop_sw_cfg_gio2                      0x00000005
#define regk_iop_sw_cfg_gio3                      0x00000002
#define regk_iop_sw_cfg_gio4                      0x00000006
#define regk_iop_sw_cfg_gio5                      0x00000003
#define regk_iop_sw_cfg_gio6                      0x00000007
#define regk_iop_sw_cfg_gio7                      0x00000004
#define regk_iop_sw_cfg_gio_in0                   0x00000000
#define regk_iop_sw_cfg_gio_in1                   0x00000001
#define regk_iop_sw_cfg_gio_in10                  0x00000002
#define regk_iop_sw_cfg_gio_in11                  0x00000003
#define regk_iop_sw_cfg_gio_in14                  0x00000004
#define regk_iop_sw_cfg_gio_in15                  0x00000005
#define regk_iop_sw_cfg_gio_in18                  0x00000002
#define regk_iop_sw_cfg_gio_in19                  0x00000003
#define regk_iop_sw_cfg_gio_in20                  0x00000004
#define regk_iop_sw_cfg_gio_in21                  0x00000005
#define regk_iop_sw_cfg_gio_in26                  0x00000006
#define regk_iop_sw_cfg_gio_in27                  0x00000007
#define regk_iop_sw_cfg_gio_in28                  0x00000006
#define regk_iop_sw_cfg_gio_in29                  0x00000007
#define regk_iop_sw_cfg_gio_in4                   0x00000000
#define regk_iop_sw_cfg_gio_in5                   0x00000001
#define regk_iop_sw_cfg_last_timer_grp0_tmr2      0x00000001
#define regk_iop_sw_cfg_last_timer_grp1_tmr2      0x00000001
#define regk_iop_sw_cfg_last_timer_grp2_tmr2      0x00000002
#define regk_iop_sw_cfg_last_timer_grp2_tmr3      0x00000003
#define regk_iop_sw_cfg_last_timer_grp3_tmr2      0x00000002
#define regk_iop_sw_cfg_last_timer_grp3_tmr3      0x00000003
#define regk_iop_sw_cfg_mpu                       0x00000001
#define regk_iop_sw_cfg_none                      0x00000000
#define regk_iop_sw_cfg_par0                      0x00000000
#define regk_iop_sw_cfg_par1                      0x00000001
#define regk_iop_sw_cfg_pdp_out0                  0x00000002
#define regk_iop_sw_cfg_pdp_out0_hi               0x00000001
#define regk_iop_sw_cfg_pdp_out0_hi_rot8          0x00000005
#define regk_iop_sw_cfg_pdp_out0_lo               0x00000000
#define regk_iop_sw_cfg_pdp_out0_lo_rot8          0x00000004
#define regk_iop_sw_cfg_pdp_out1                  0x00000003
#define regk_iop_sw_cfg_pdp_out1_hi               0x00000003