iop_sw_cfg_defs_asm.h

linux-2.6.15.6

#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148

/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
#define reg_iop_sw_cfg_rw_gio_mask_offset 152

/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156

/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
#define reg_iop_sw_cfg_rw_pinmapping_offset 160

/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164

/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168

/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172

/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176

/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180

/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184

/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188

/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192

/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196

/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200

/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204

/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8