iop_sw_cfg_defs_asm.h

linux-2.6.15.6

#ifndef __iop_sw_cfg_defs_asm_h
#define __iop_sw_cfg_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
 *     id:           <not found>
 *     last modfied: Mon Apr 11 16:10:19 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
 *      id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0

/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4

/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8

/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12

/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16

/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20

/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24

/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28

/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32

/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36

/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40

/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44

/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48

/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52

/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56

/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60

/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64

/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68

/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72

/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76

/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_spu0_owner_offset 80

/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_spu1_owner_offset 84

/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88

/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92

/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96

/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100

/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104

/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108

/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112

/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116

/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120

/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124

/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128

/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132

/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
#define reg_iop_sw_cfg_rw_bus0_mask_offset 136

/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140

/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
#define reg_iop_sw_cfg_rw_bus1_mask_offset 144

/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0