iop_spu_defs_asm.h

linux-2.6.15.6

#ifndef __iop_spu_defs_asm_h
#define __iop_spu_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/iop_spu.r
 *     id:           <not found>
 *     last modfied: Mon Apr 11 16:08:46 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
 *      id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

#define STRIDE_iop_spu_rw_r 4
/* Register rw_r, scope iop_spu, type rw */
#define reg_iop_spu_rw_r_offset 0

/* Register rw_seq_pc, scope iop_spu, type rw */
#define reg_iop_spu_rw_seq_pc___addr___lsb 0
#define reg_iop_spu_rw_seq_pc___addr___width 12
#define reg_iop_spu_rw_seq_pc_offset 64

/* Register rw_fsm_pc, scope iop_spu, type rw */
#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
#define reg_iop_spu_rw_fsm_pc___addr___width 12
#define reg_iop_spu_rw_fsm_pc_offset 68

/* Register rw_ctrl, scope iop_spu, type rw */
#define reg_iop_spu_rw_ctrl___fsm___lsb 0
#define reg_iop_spu_rw_ctrl___fsm___width 1
#define reg_iop_spu_rw_ctrl___fsm___bit 0
#define reg_iop_spu_rw_ctrl___en___lsb 1
#define reg_iop_spu_rw_ctrl___en___width 1
#define reg_iop_spu_rw_ctrl___en___bit 1
#define reg_iop_spu_rw_ctrl_offset 72

/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
#define reg_iop_spu_rw_fsm_inputs3_0_offset 76

/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
#define reg_iop_spu_rw_fsm_inputs7_4_offset 80

/* Register rw_gio_out, scope iop_spu, type rw */
#define reg_iop_spu_rw_gio_out_offset 84

/* Register rw_bus0_out, scope iop_spu, type rw */
#define reg_iop_spu_rw_bus0_out_offset 88

/* Register rw_bus1_out, scope iop_spu, type rw */
#define reg_iop_spu_rw_bus1_out_offset 92

/* Register r_gio_in, scope iop_spu, type r */
#define reg_iop_spu_r_gio_in_offset 96

/* Register r_bus0_in, scope iop_spu, type r */
#define reg_iop_spu_r_bus0_in_offset 100

/* Register r_bus1_in, scope iop_spu, type r */
#define reg_iop_spu_r_bus1_in_offset 104

/* Register rw_gio_out_set, scope iop_spu, type rw */
#define reg_iop_spu_rw_gio_out_set_offset 108

/* Register rw_gio_out_clr, scope iop_spu, type rw */
#define reg_iop_spu_rw_gio_out_clr_offset 112

/* Register rs_wr_stat, scope iop_spu, type rs */
#define reg_iop_spu_rs_wr_stat___r0___lsb 0
#define reg_iop_spu_rs_wr_stat___r0___width 1
#define reg_iop_spu_rs_wr_stat___r0___bit 0
#define reg_iop_spu_rs_wr_stat___r1___lsb 1
#define reg_iop_spu_rs_wr_stat___r1___width 1
#define reg_iop_spu_rs_wr_stat___r1___bit 1
#define reg_iop_spu_rs_wr_stat___r2___lsb 2
#define reg_iop_spu_rs_wr_stat___r2___width 1
#define reg_iop_spu_rs_wr_stat___r2___bit 2
#define reg_iop_spu_rs_wr_stat___r3___lsb 3
#define reg_iop_spu_rs_wr_stat___r3___width 1
#define reg_iop_spu_rs_wr_stat___r3___bit 3
#define reg_iop_spu_rs_wr_stat___r4___lsb 4
#define reg_iop_spu_rs_wr_stat___r4___width 1
#define reg_iop_spu_rs_wr_stat___r4___bit 4
#define reg_iop_spu_rs_wr_stat___r5___lsb 5
#define reg_iop_spu_rs_wr_stat___r5___width 1
#define reg_iop_spu_rs_wr_stat___r5___bit 5
#define reg_iop_spu_rs_wr_stat___r6___lsb 6
#define reg_iop_spu_rs_wr_stat___r6___width 1
#define reg_iop_spu_rs_wr_stat___r6___bit 6
#define reg_iop_spu_rs_wr_stat___r7___lsb 7
#define reg_iop_spu_rs_wr_stat___r7___width 1
#define reg_iop_spu_rs_wr_stat___r7___bit 7
#define reg_iop_spu_rs_wr_stat___r8___lsb 8
#define reg_iop_spu_rs_wr_stat___r8___width 1
#define reg_iop_spu_rs_wr_stat___r8___bit 8
#define reg_iop_spu_rs_wr_stat___r9___lsb 9
#define reg_iop_spu_rs_wr_stat___r9___width 1
#define reg_iop_spu_rs_wr_stat___r9___bit 9
#define reg_iop_spu_rs_wr_stat___r10___lsb 10
#define reg_iop_spu_rs_wr_stat___r10___width 1
#define reg_iop_spu_rs_wr_stat___r10___bit 10
#define reg_iop_spu_rs_wr_stat___r11___lsb 11
#define reg_iop_spu_rs_wr_stat___r11___width 1
#define reg_iop_spu_rs_wr_stat___r11___bit 11
#define reg_iop_spu_rs_wr_stat___r12___lsb 12
#define reg_iop_spu_rs_wr_stat___r12___width 1
#define reg_iop_spu_rs_wr_stat___r12___bit 12
#define reg_iop_spu_rs_wr_stat___r13___lsb 13
#define reg_iop_spu_rs_wr_stat___r13___width 1
#define reg_iop_spu_rs_wr_stat___r13___bit 13
#define reg_iop_spu_rs_wr_stat___r14___lsb 14
#define reg_iop_spu_rs_wr_stat___r14___width 1
#define reg_iop_spu_rs_wr_stat___r14___bit 14
#define reg_iop_spu_rs_wr_stat___r15___lsb 15
#define reg_iop_spu_rs_wr_stat___r15___width 1
#define reg_iop_spu_rs_wr_stat___r15___bit 15
#define reg_iop_spu_rs_wr_stat_offset 116

/* Register r_wr_stat, scope iop_spu, type r */
#define reg_iop_spu_r_wr_stat___r0___lsb 0
#define reg_iop_spu_r_wr_stat___r0___width 1
#define reg_iop_spu_r_wr_stat___r0___bit 0
#define reg_iop_spu_r_wr_stat___r1___lsb 1
#define reg_iop_spu_r_wr_stat___r1___width 1
#define reg_iop_spu_r_wr_stat___r1___bit 1
#define reg_iop_spu_r_wr_stat___r2___lsb 2
#define reg_iop_spu_r_wr_stat___r2___width 1
#define reg_iop_spu_r_wr_stat___r2___bit 2
#define reg_iop_spu_r_wr_stat___r3___lsb 3
#define reg_iop_spu_r_wr_stat___r3___width 1
#define reg_iop_spu_r_wr_stat___r3___bit 3
#define reg_iop_spu_r_wr_stat___r4___lsb 4
#define reg_iop_spu_r_wr_stat___r4___width 1
#define reg_iop_spu_r_wr_stat___r4___bit 4
#define reg_iop_spu_r_wr_stat___r5___lsb 5
#define reg_iop_spu_r_wr_stat___r5___width 1
#define reg_iop_spu_r_wr_stat___r5___bit 5
#define reg_iop_spu_r_wr_stat___r6___lsb 6
#define reg_iop_spu_r_wr_stat___r6___width 1
#define reg_iop_spu_r_wr_stat___r6___bit 6
#define reg_iop_spu_r_wr_stat___r7___lsb 7
#define reg_iop_spu_r_wr_stat___r7___width 1
#define reg_iop_spu_r_wr_stat___r7___bit 7
#define reg_iop_spu_r_wr_stat___r8___lsb 8
#define reg_iop_spu_r_wr_stat___r8___width 1
#define reg_iop_spu_r_wr_stat___r8___bit 8
#define reg_iop_spu_r_wr_stat___r9___lsb 9
#define reg_iop_spu_r_wr_stat___r9___width 1
#define reg_iop_spu_r_wr_stat___r9___bit 9
#define reg_iop_spu_r_wr_stat___r10___lsb 10
#define reg_iop_spu_r_wr_stat___r10___width 1
#define reg_iop_spu_r_wr_stat___r10___bit 10
#define reg_iop_spu_r_wr_stat___r11___lsb 11
#define reg_iop_spu_r_wr_stat___r11___width 1
#define reg_iop_spu_r_wr_stat___r11___bit 11
#define reg_iop_spu_r_wr_stat___r12___lsb 12
#define reg_iop_spu_r_wr_stat___r12___width 1
#define reg_iop_spu_r_wr_stat___r12___bit 12
#define reg_iop_spu_r_wr_stat___r13___lsb 13
#define reg_iop_spu_r_wr_stat___r13___width 1
#define reg_iop_spu_r_wr_stat___r13___bit 13
#define reg_iop_spu_r_wr_stat___r14___lsb 14
#define reg_iop_spu_r_wr_stat___r14___width 1
#define reg_iop_spu_r_wr_stat___r14___bit 14
#define reg_iop_spu_r_wr_stat___r15___lsb 15
#define reg_iop_spu_r_wr_stat___r15___width 1
#define reg_iop_spu_r_wr_stat___r15___bit 15
#define reg_iop_spu_r_wr_stat_offset 120

/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124

/* Register r_stat_in, scope iop_spu, type r */
#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20