iop_sw_spu_defs.h

linux-2.6.15.6

  unsigned int byte1 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus0_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92

/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus0_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96

/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus1_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100

/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus1_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104

/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus1_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108

/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus1_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112

/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116

/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120

/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124

/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128

/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132

/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136

/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140

/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144

/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int intr0  : 1;
  unsigned int intr1  : 1;
  unsigned int intr2  : 1;
  unsigned int intr3  : 1;
  unsigned int intr4  : 1;
  unsigned int intr5  : 1;
  unsigned int intr6  : 1;
  unsigned int intr7  : 1;
  unsigned int intr8  : 1;
  unsigned int intr9  : 1;
  unsigned int intr10 : 1;
  unsigned int intr11 : 1;
  unsigned int intr12 : 1;
  unsigned int intr13 : 1;
  unsigned int intr14 : 1;
  unsigned int intr15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_cpu_intr;
#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148

/* Register r_cpu_intr, scope iop_sw_spu, type r */
typedef struct {
  unsigned int intr0  : 1;
  unsigned int intr1  : 1;
  unsigned int intr2  : 1;
  unsigned int intr3  : 1;
  unsigned int intr4  : 1;
  unsigned int intr5  : 1;
  unsigned int intr6  : 1;
  unsigned int intr7  : 1;
  unsigned int intr8  : 1;
  unsigned int intr9  : 1;
  unsigned int intr10 : 1;
  unsigned int intr11 : 1;
  unsigned int intr12 : 1;
  unsigned int intr13 : 1;
  unsigned int intr14 : 1;
  unsigned int intr15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_r_cpu_intr;
#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152

/* Register r_hw_intr, scope iop_sw_spu, type r */
typedef struct {
  unsigned int trigger_grp0    : 1;
  unsigned int trigger_grp1    : 1;
  unsigned int trigger_grp2    : 1;
  unsigned int trigger_grp3    : 1;
  unsigned int trigger_grp4    : 1;
  unsigned int trigger_grp5    : 1;
  unsigned int trigger_grp6    : 1;
  unsigned int trigger_grp7    : 1;
  unsigned int timer_grp0      : 1;
  unsigned int timer_grp1      : 1;
  unsigned int timer_grp2      : 1;
  unsigned int timer_grp3      : 1;
  unsigned int fifo_out0       : 1;
  unsigned int fifo_out0_extra : 1;
  unsigned int fifo_in0        : 1;
  unsigned int fifo_in0_extra  : 1;
  unsigned int fifo_out1       : 1;
  unsigned int fifo_out1_extra : 1;
  unsigned int fifo_in1        : 1;
  unsigned int fifo_in1_extra  : 1;
  unsigned int dmc_out0        : 1;
  unsigned int dmc_in0         : 1;
  unsigned int dmc_out1        : 1;
  unsigned int dmc_in1         : 1;
  unsigned int dummy1          : 8;
} reg_iop_sw_spu_r_hw_intr;
#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156

/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int intr0  : 1;
  unsigned int intr1  : 1;
  unsigned int intr2  : 1;
  unsigned int intr3  : 1;
  unsigned int intr4  : 1;
  unsigned int intr5  : 1;
  unsigned int intr6  : 1;
  unsigned int intr7  : 1;
  unsigned int intr8  : 1;
  unsigned int intr9  : 1;
  unsigned int intr10 : 1;
  unsigned int intr11 : 1;
  unsigned int intr12 : 1;
  unsigned int intr13 : 1;
  unsigned int intr14 : 1;
  unsigned int intr15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_mpu_intr;
#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160

/* Register r_mpu_intr, scope iop_sw_spu, type r */
typedef struct {
  unsigned int intr0            : 1;
  unsigned int intr1            : 1;
  unsigned int intr2            : 1;
  unsigned int intr3            : 1;
  unsigned int intr4            : 1;
  unsigned int intr5            : 1;
  unsigned int intr6            : 1;
  unsigned int intr7            : 1;
  unsigned int intr8            : 1;
  unsigned int intr9            : 1;
  unsigned int intr10           : 1;
  unsigned int intr11           : 1;
  unsigned int intr12           : 1;
  unsigned int intr13           : 1;
  unsigned int intr14           : 1;
  unsigned int intr15           : 1;
  unsigned int other_spu_intr0  : 1;
  unsigned int other_spu_intr1  : 1;
  unsigned int other_spu_intr2  : 1;
  unsigned int other_spu_intr3  : 1;
  unsigned int other_spu_intr4  : 1;
  unsigned int other_spu_intr5  : 1;
  unsigned int other_spu_intr6  : 1;
  unsigned int other_spu_intr7  : 1;
  unsigned int other_spu_intr8  : 1;
  unsigned int other_spu_intr9  : 1;
  unsigned int other_spu_intr10 : 1;
  unsigned int other_spu_intr11 : 1;
  unsigned int other_spu_intr12 : 1;
  unsigned int other_spu_intr13 : 1;
  unsigned int other_spu_intr14 : 1;
  unsigned int other_spu_intr15 : 1;
} reg_iop_sw_spu_r_mpu_intr;
#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164


/* Constants */
enum {
  regk_iop_sw_spu_copy                     = 0x00000000,
  regk_iop_sw_spu_no                       = 0x00000000,
  regk_iop_sw_spu_nop                      = 0x00000000,
  regk_iop_sw_spu_rd                       = 0x00000002,
  regk_iop_sw_spu_reg_copy                 = 0x00000001,
  regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
  regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
  regk_iop_sw_spu_set                      = 0x00000001,
  regk_iop_sw_spu_wr                       = 0x00000003,
  regk_iop_sw_spu_yes                      = 0x00000001
};
#endif /* __iop_sw_spu_defs_h */