iop_sw_spu_defs.h

linux-2.6.15.6

#ifndef __iop_sw_spu_defs_h
#define __iop_sw_spu_defs_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
 *     id:           <not found>
 *     last modfied: Mon Apr 11 16:10:19 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
 *      id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope iop_sw_spu */

/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int keep_owner  : 1;
  unsigned int cmd         : 2;
  unsigned int size        : 3;
  unsigned int wr_spu0_mem : 1;
  unsigned int wr_spu1_mem : 1;
  unsigned int dummy1      : 24;
} reg_iop_sw_spu_rw_mc_ctrl;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0

/* Register rw_mc_data, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_mc_data;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4

/* Register rw_mc_addr, scope iop_sw_spu, type rw */
typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8

/* Register rs_mc_data, scope iop_sw_spu, type rs */
typedef unsigned int reg_iop_sw_spu_rs_mc_data;
#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12

/* Register r_mc_data, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_mc_data;
#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16

/* Register r_mc_stat, scope iop_sw_spu, type r */
typedef struct {
  unsigned int busy_cpu      : 1;
  unsigned int busy_mpu      : 1;
  unsigned int busy_spu0     : 1;
  unsigned int busy_spu1     : 1;
  unsigned int owned_by_cpu  : 1;
  unsigned int owned_by_mpu  : 1;
  unsigned int owned_by_spu0 : 1;
  unsigned int owned_by_spu1 : 1;
  unsigned int dummy1        : 24;
} reg_iop_sw_spu_r_mc_stat;
#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20

/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus0_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24

/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus0_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28

/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 1;
  unsigned int byte1 : 1;
  unsigned int byte2 : 1;
  unsigned int byte3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus0_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32

/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 1;
  unsigned int byte1 : 1;
  unsigned int byte2 : 1;
  unsigned int byte3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus0_oe_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36

/* Register r_bus0_in, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_bus0_in;
#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40

/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus1_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44

/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus1_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48

/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 1;
  unsigned int byte1 : 1;
  unsigned int byte2 : 1;
  unsigned int byte3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus1_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52

/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 1;
  unsigned int byte1 : 1;
  unsigned int byte2 : 1;
  unsigned int byte3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus1_oe_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56

/* Register r_bus1_in, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_bus1_in;
#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60

/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64

/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68

/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72

/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_oe_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76

/* Register r_gio_in, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_gio_in;
#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80

/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus0_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84

/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus0_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88

/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;