iop_mpu_macros.h

linux-2.6.15.6

#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_RET() (0x63003000)

#define MPU_RETI() (0x63602800)

#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
                            | ((D & ((1 << 5) - 1)) << 21))

#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 5) - 1)) << 21))

#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
                            | ((D & ((1 << 11) - 1)) << 0))

#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
                            | ((D & ((1 << 5) - 1)) << 16))

#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
                             | ((D & ((1 << 11) - 1)) << 0))

#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
                             | ((D & ((1 << 5) - 1)) << 16))

#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))

#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)

#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))

#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)

#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
                                 | ((N & ((1 << 16) - 1)) << 0)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 16) - 1)) << 0))

#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 16) - 1)) << 0))

#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))

#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)

#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)

#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)

#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
                                      | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
                                      | ((D & ((1 << 5) - 1)) << 11))

#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
                                 | ((N & ((1 << 16) - 1)) << 0)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
                                 | ((N & ((1 << 5) - 1)) << 16)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)


#endif /* end of __IOP_MPU_MACROS_H__ */
/* End of iop_mpu_macros.h */