iop_mpu_macros.h

linux-2.6.15.6

#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))

#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))

#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))

#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 21)\
                                | ((D & ((1 << 16) - 1)) << 0))

#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 21)\
                                | ((D & ((1 << 16) - 1)) << 0))

#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
                             | ((D & ((1 << 16) - 1)) << 0))

#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
                             | ((D & ((1 << 16) - 1)) << 0))

#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
                             | ((D & ((1 << 16) - 1)) << 0))

#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
                            | ((D & ((1 << 16) - 1)) << 0))

#define MPU_DI() (0x40000001)

#define MPU_EI() (0x40000003)

#define MPU_HALT() (0x40000002)

#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))

#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))

#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))

#define MPU_JNT() (0x61000000)

#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))

#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))

#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))

#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
                                 | ((N & ((1 << 16) - 1)) << 0)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
                                 | ((N & ((1 << 16) - 1)) << 0)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
                            | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
                            | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
                            | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
                            | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
                            | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
                            | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 16))

#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
                               | ((N & ((1 << 8) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 16))

#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
                              | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
                              | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
                              | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
                              | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)

#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)

#define MPU_NOP() (0x40000000)

#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
                             | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
                               | ((N & ((1 << 5) - 1)) << 11)\
                               | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 16) - 1)) << 0)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
                                | ((N & ((1 << 5) - 1)) << 16)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
                                      | ((D & ((1 << 5) - 1)) << 21))