iop_mpu_macros.h

linux-2.6.15.6

/* ************************************************************************* */
/* This file is autogenerated by IOPASM Version 1.2                          */
/* DO NOT EDIT THIS FILE - All changes will be lost!                         */
/* ************************************************************************* */



#ifndef __IOP_MPU_MACROS_H__
#define __IOP_MPU_MACROS_H__


/* ************************************************************************* */
/*                           REGISTER DEFINITIONS                            */
/* ************************************************************************* */
#define MPU_R0 (0x0)
#define MPU_R1 (0x1)
#define MPU_R2 (0x2)
#define MPU_R3 (0x3)
#define MPU_R4 (0x4)
#define MPU_R5 (0x5)
#define MPU_R6 (0x6)
#define MPU_R7 (0x7)
#define MPU_R8 (0x8)
#define MPU_R9 (0x9)
#define MPU_R10 (0xa)
#define MPU_R11 (0xb)
#define MPU_R12 (0xc)
#define MPU_R13 (0xd)
#define MPU_R14 (0xe)
#define MPU_R15 (0xf)
#define MPU_PC (0x2)
#define MPU_WSTS (0x3)
#define MPU_JADDR (0x4)
#define MPU_IRP (0x5)
#define MPU_SRP (0x6)
#define MPU_T0 (0x8)
#define MPU_T1 (0x9)
#define MPU_T2 (0xa)
#define MPU_T3 (0xb)
#define MPU_I0 (0x10)
#define MPU_I1 (0x11)
#define MPU_I2 (0x12)
#define MPU_I3 (0x13)
#define MPU_I4 (0x14)
#define MPU_I5 (0x15)
#define MPU_I6 (0x16)
#define MPU_I7 (0x17)
#define MPU_I8 (0x18)
#define MPU_I9 (0x19)
#define MPU_I10 (0x1a)
#define MPU_I11 (0x1b)
#define MPU_I12 (0x1c)
#define MPU_I13 (0x1d)
#define MPU_I14 (0x1e)
#define MPU_I15 (0x1f)
#define MPU_P2 (0x2)
#define MPU_P3 (0x3)
#define MPU_P5 (0x5)
#define MPU_P6 (0x6)
#define MPU_P8 (0x8)
#define MPU_P9 (0x9)
#define MPU_P10 (0xa)
#define MPU_P11 (0xb)
#define MPU_P16 (0x10)
#define MPU_P17 (0x12)
#define MPU_P18 (0x12)
#define MPU_P19 (0x13)
#define MPU_P20 (0x14)
#define MPU_P21 (0x15)
#define MPU_P22 (0x16)
#define MPU_P23 (0x17)
#define MPU_P24 (0x18)
#define MPU_P25 (0x19)
#define MPU_P26 (0x1a)
#define MPU_P27 (0x1b)
#define MPU_P28 (0x1c)
#define MPU_P29 (0x1d)
#define MPU_P30 (0x1e)
#define MPU_P31 (0x1f)
#define MPU_P1 (0x1)
#define MPU_REGA (0x1)



/* ************************************************************************* */
/*                              ADDRESS MACROS                               */
/* ************************************************************************* */
#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
#define MK_BYTE_ADDR(ADDR) (ADDR)



/* ************************************************************************* */
/*                            INSTRUCTION MACROS                             */
/* ************************************************************************* */
#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
                                 | ((N & ((1 << 16) - 1)) << 0)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
                                 | ((N & ((1 << 5) - 1)) << 16)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
                                | ((N & ((1 << 5) - 1)) << 11)\
                                | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
                                 | ((N & ((1 << 16) - 1)) << 0)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
                                 | ((N & ((1 << 5) - 1)) << 16)\
                                 | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)

#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)

#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
                                       | ((D & ((1 << 5) - 1)) << 21))

#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)