📄 iop_sw_cpu_defs.h
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unsigned int spu0_11 : 1; unsigned int spu0_12 : 1; unsigned int spu0_13 : 1; unsigned int spu0_14 : 1; unsigned int spu0_15 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1;} reg_iop_sw_cpu_rw_intr1_mask;#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int mpu_24 : 1; unsigned int mpu_25 : 1; unsigned int mpu_26 : 1; unsigned int mpu_27 : 1; unsigned int mpu_28 : 1; unsigned int mpu_29 : 1; unsigned int mpu_30 : 1; unsigned int mpu_31 : 1; unsigned int spu0_8 : 1; unsigned int spu0_9 : 1; unsigned int spu0_10 : 1; unsigned int spu0_11 : 1; unsigned int spu0_12 : 1; unsigned int spu0_13 : 1; unsigned int spu0_14 : 1; unsigned int spu0_15 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1;} reg_iop_sw_cpu_rw_ack_intr1;#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104/* Register r_intr1, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int mpu_24 : 1; unsigned int mpu_25 : 1; unsigned int mpu_26 : 1; unsigned int mpu_27 : 1; unsigned int mpu_28 : 1; unsigned int mpu_29 : 1; unsigned int mpu_30 : 1; unsigned int mpu_31 : 1; unsigned int spu0_8 : 1; unsigned int spu0_9 : 1; unsigned int spu0_10 : 1; unsigned int spu0_11 : 1; unsigned int spu0_12 : 1; unsigned int spu0_13 : 1; unsigned int spu0_14 : 1; unsigned int spu0_15 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1;} reg_iop_sw_cpu_r_intr1;#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108/* Register r_masked_intr1, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int mpu_24 : 1; unsigned int mpu_25 : 1; unsigned int mpu_26 : 1; unsigned int mpu_27 : 1; unsigned int mpu_28 : 1; unsigned int mpu_29 : 1; unsigned int mpu_30 : 1; unsigned int mpu_31 : 1; unsigned int spu0_8 : 1; unsigned int spu0_9 : 1; unsigned int spu0_10 : 1; unsigned int spu0_11 : 1; unsigned int spu0_12 : 1; unsigned int spu0_13 : 1; unsigned int spu0_14 : 1; unsigned int spu0_15 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1;} reg_iop_sw_cpu_r_masked_intr1;#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */typedef struct { unsigned int mpu_0 : 1; unsigned int mpu_1 : 1; unsigned int mpu_2 : 1; unsigned int mpu_3 : 1; unsigned int mpu_4 : 1; unsigned int mpu_5 : 1; unsigned int mpu_6 : 1; unsigned int mpu_7 : 1; unsigned int spu0_0 : 1; unsigned int spu0_1 : 1; unsigned int spu0_2 : 1; unsigned int spu0_3 : 1; unsigned int spu0_4 : 1; unsigned int spu0_5 : 1; unsigned int spu0_6 : 1; unsigned int spu0_7 : 1; unsigned int dmc_in0 : 1; unsigned int dmc_out0 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_in0_extra : 1; unsigned int fifo_out0_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int timer_grp1 : 1;} reg_iop_sw_cpu_rw_intr2_mask;#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */typedef struct { unsigned int mpu_0 : 1; unsigned int mpu_1 : 1; unsigned int mpu_2 : 1; unsigned int mpu_3 : 1; unsigned int mpu_4 : 1; unsigned int mpu_5 : 1; unsigned int mpu_6 : 1; unsigned int mpu_7 : 1; unsigned int spu0_0 : 1; unsigned int spu0_1 : 1; unsigned int spu0_2 : 1; unsigned int spu0_3 : 1; unsigned int spu0_4 : 1; unsigned int spu0_5 : 1; unsigned int spu0_6 : 1; unsigned int spu0_7 : 1; unsigned int dummy1 : 16;} reg_iop_sw_cpu_rw_ack_intr2;#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120/* Register r_intr2, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_0 : 1; unsigned int mpu_1 : 1; unsigned int mpu_2 : 1; unsigned int mpu_3 : 1; unsigned int mpu_4 : 1; unsigned int mpu_5 : 1; unsigned int mpu_6 : 1; unsigned int mpu_7 : 1; unsigned int spu0_0 : 1; unsigned int spu0_1 : 1; unsigned int spu0_2 : 1; unsigned int spu0_3 : 1; unsigned int spu0_4 : 1; unsigned int spu0_5 : 1; unsigned int spu0_6 : 1; unsigned int spu0_7 : 1; unsigned int dmc_in0 : 1; unsigned int dmc_out0 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_in0_extra : 1; unsigned int fifo_out0_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int timer_grp1 : 1;} reg_iop_sw_cpu_r_intr2;#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124/* Register r_masked_intr2, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_0 : 1; unsigned int mpu_1 : 1; unsigned int mpu_2 : 1; unsigned int mpu_3 : 1; unsigned int mpu_4 : 1; unsigned int mpu_5 : 1; unsigned int mpu_6 : 1; unsigned int mpu_7 : 1; unsigned int spu0_0 : 1; unsigned int spu0_1 : 1; unsigned int spu0_2 : 1; unsigned int spu0_3 : 1; unsigned int spu0_4 : 1; unsigned int spu0_5 : 1; unsigned int spu0_6 : 1; unsigned int spu0_7 : 1; unsigned int dmc_in0 : 1; unsigned int dmc_out0 : 1; unsigned int fifo_in0 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_in0_extra : 1; unsigned int fifo_out0_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int timer_grp1 : 1;} reg_iop_sw_cpu_r_masked_intr2;#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1; unsigned int dmc_in1 : 1; unsigned int dmc_out1 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_in1_extra : 1; unsigned int fifo_out1_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp2 : 1; unsigned int timer_grp3 : 1;} reg_iop_sw_cpu_rw_intr3_mask;#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1; unsigned int dummy1 : 16;} reg_iop_sw_cpu_rw_ack_intr3;#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136/* Register r_intr3, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1; unsigned int dmc_in1 : 1; unsigned int dmc_out1 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_in1_extra : 1; unsigned int fifo_out1_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp2 : 1; unsigned int timer_grp3 : 1;} reg_iop_sw_cpu_r_intr3;#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140/* Register r_masked_intr3, scope iop_sw_cpu, type r */typedef struct { unsigned int mpu_16 : 1; unsigned int mpu_17 : 1; unsigned int mpu_18 : 1; unsigned int mpu_19 : 1; unsigned int mpu_20 : 1; unsigned int mpu_21 : 1; unsigned int mpu_22 : 1; unsigned int mpu_23 : 1; unsigned int spu1_0 : 1; unsigned int spu1_1 : 1; unsigned int spu1_2 : 1; unsigned int spu1_3 : 1; unsigned int spu1_4 : 1; unsigned int spu1_5 : 1; unsigned int spu1_6 : 1; unsigned int spu1_7 : 1; unsigned int dmc_in1 : 1; unsigned int dmc_out1 : 1; unsigned int fifo_in1 : 1; unsigned int fifo_out1 : 1; unsigned int fifo_in1_extra : 1; unsigned int fifo_out1_extra : 1; unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp2 : 1; unsigned int timer_grp3 : 1;} reg_iop_sw_cpu_r_masked_intr3;#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144/* Constants */enum { regk_iop_sw_cpu_copy = 0x00000000, regk_iop_sw_cpu_no = 0x00000000, regk_iop_sw_cpu_rd = 0x00000002, regk_iop_sw_cpu_reg_copy = 0x00000001, regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, regk_iop_sw_cpu_wr = 0x00000003, regk_iop_sw_cpu_yes = 0x00000001};#endif /* __iop_sw_cpu_defs_h */⌨️ 快捷键说明
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