sv_addr.agh

linux-2.6.15.6

#define R_SERIAL0_READ__overrun__yes 1
#define R_SERIAL0_READ__par_err__BITNR 10
#define R_SERIAL0_READ__par_err__WIDTH 1
#define R_SERIAL0_READ__par_err__no 0
#define R_SERIAL0_READ__par_err__yes 1
#define R_SERIAL0_READ__framing_err__BITNR 9
#define R_SERIAL0_READ__framing_err__WIDTH 1
#define R_SERIAL0_READ__framing_err__no 0
#define R_SERIAL0_READ__framing_err__yes 1
#define R_SERIAL0_READ__data_avail__BITNR 8
#define R_SERIAL0_READ__data_avail__WIDTH 1
#define R_SERIAL0_READ__data_avail__no 0
#define R_SERIAL0_READ__data_avail__yes 1
#define R_SERIAL0_READ__data_in__BITNR 0
#define R_SERIAL0_READ__data_in__WIDTH 8

#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061)
#define R_SERIAL0_STATUS__xoff_detect__BITNR 7
#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1
#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0
#define R_SERIAL0_STATUS__xoff_detect__xoff 1
#define R_SERIAL0_STATUS__cts___BITNR 6
#define R_SERIAL0_STATUS__cts___WIDTH 1
#define R_SERIAL0_STATUS__cts___active 0
#define R_SERIAL0_STATUS__cts___inactive 1
#define R_SERIAL0_STATUS__tr_ready__BITNR 5
#define R_SERIAL0_STATUS__tr_ready__WIDTH 1
#define R_SERIAL0_STATUS__tr_ready__full 0
#define R_SERIAL0_STATUS__tr_ready__ready 1
#define R_SERIAL0_STATUS__rxd__BITNR 4
#define R_SERIAL0_STATUS__rxd__WIDTH 1
#define R_SERIAL0_STATUS__overrun__BITNR 3
#define R_SERIAL0_STATUS__overrun__WIDTH 1
#define R_SERIAL0_STATUS__overrun__no 0
#define R_SERIAL0_STATUS__overrun__yes 1
#define R_SERIAL0_STATUS__par_err__BITNR 2
#define R_SERIAL0_STATUS__par_err__WIDTH 1
#define R_SERIAL0_STATUS__par_err__no 0
#define R_SERIAL0_STATUS__par_err__yes 1
#define R_SERIAL0_STATUS__framing_err__BITNR 1
#define R_SERIAL0_STATUS__framing_err__WIDTH 1
#define R_SERIAL0_STATUS__framing_err__no 0
#define R_SERIAL0_STATUS__framing_err__yes 1
#define R_SERIAL0_STATUS__data_avail__BITNR 0
#define R_SERIAL0_STATUS__data_avail__WIDTH 1
#define R_SERIAL0_STATUS__data_avail__no 0
#define R_SERIAL0_STATUS__data_avail__yes 1

#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060)
#define R_SERIAL0_REC_DATA__data_in__BITNR 0
#define R_SERIAL0_REC_DATA__data_in__WIDTH 8

#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064)
#define R_SERIAL0_XOFF__tx_stop__BITNR 9
#define R_SERIAL0_XOFF__tx_stop__WIDTH 1
#define R_SERIAL0_XOFF__tx_stop__enable 0
#define R_SERIAL0_XOFF__tx_stop__stop 1
#define R_SERIAL0_XOFF__auto_xoff__BITNR 8
#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1
#define R_SERIAL0_XOFF__auto_xoff__disable 0
#define R_SERIAL0_XOFF__auto_xoff__enable 1
#define R_SERIAL0_XOFF__xoff_char__BITNR 0
#define R_SERIAL0_XOFF__xoff_char__WIDTH 8

#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
#define R_SERIAL1_CTRL__tr_baud__BITNR 28
#define R_SERIAL1_CTRL__tr_baud__WIDTH 4
#define R_SERIAL1_CTRL__tr_baud__c300Hz 0
#define R_SERIAL1_CTRL__tr_baud__c600Hz 1
#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2
#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3
#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4
#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5
#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6
#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7
#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8
#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9
#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10
#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11
#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12
#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13
#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14
#define R_SERIAL1_CTRL__tr_baud__reserved 15
#define R_SERIAL1_CTRL__rec_baud__BITNR 24
#define R_SERIAL1_CTRL__rec_baud__WIDTH 4
#define R_SERIAL1_CTRL__rec_baud__c300Hz 0
#define R_SERIAL1_CTRL__rec_baud__c600Hz 1
#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2
#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3
#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4
#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5
#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6
#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7
#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8
#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9
#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10
#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11
#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12
#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13
#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14
#define R_SERIAL1_CTRL__rec_baud__reserved 15
#define R_SERIAL1_CTRL__dma_err__BITNR 23
#define R_SERIAL1_CTRL__dma_err__WIDTH 1
#define R_SERIAL1_CTRL__dma_err__stop 0
#define R_SERIAL1_CTRL__dma_err__ignore 1
#define R_SERIAL1_CTRL__rec_enable__BITNR 22
#define R_SERIAL1_CTRL__rec_enable__WIDTH 1
#define R_SERIAL1_CTRL__rec_enable__disable 0
#define R_SERIAL1_CTRL__rec_enable__enable 1
#define R_SERIAL1_CTRL__rts___BITNR 21
#define R_SERIAL1_CTRL__rts___WIDTH 1
#define R_SERIAL1_CTRL__rts___active 0
#define R_SERIAL1_CTRL__rts___inactive 1
#define R_SERIAL1_CTRL__sampling__BITNR 20
#define R_SERIAL1_CTRL__sampling__WIDTH 1
#define R_SERIAL1_CTRL__sampling__middle 0
#define R_SERIAL1_CTRL__sampling__majority 1
#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1
#define R_SERIAL1_CTRL__rec_stick_par__normal 0
#define R_SERIAL1_CTRL__rec_stick_par__stick 1
#define R_SERIAL1_CTRL__rec_par__BITNR 18
#define R_SERIAL1_CTRL__rec_par__WIDTH 1
#define R_SERIAL1_CTRL__rec_par__even 0
#define R_SERIAL1_CTRL__rec_par__odd 1
#define R_SERIAL1_CTRL__rec_par_en__BITNR 17
#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1
#define R_SERIAL1_CTRL__rec_par_en__disable 0
#define R_SERIAL1_CTRL__rec_par_en__enable 1
#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1
#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0
#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1
#define R_SERIAL1_CTRL__txd__BITNR 15
#define R_SERIAL1_CTRL__txd__WIDTH 1
#define R_SERIAL1_CTRL__tr_enable__BITNR 14
#define R_SERIAL1_CTRL__tr_enable__WIDTH 1
#define R_SERIAL1_CTRL__tr_enable__disable 0
#define R_SERIAL1_CTRL__tr_enable__enable 1
#define R_SERIAL1_CTRL__auto_cts__BITNR 13
#define R_SERIAL1_CTRL__auto_cts__WIDTH 1
#define R_SERIAL1_CTRL__auto_cts__disabled 0
#define R_SERIAL1_CTRL__auto_cts__active 1
#define R_SERIAL1_CTRL__stop_bits__BITNR 12
#define R_SERIAL1_CTRL__stop_bits__WIDTH 1
#define R_SERIAL1_CTRL__stop_bits__one_bit 0
#define R_SERIAL1_CTRL__stop_bits__two_bits 1
#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1
#define R_SERIAL1_CTRL__tr_stick_par__normal 0
#define R_SERIAL1_CTRL__tr_stick_par__stick 1
#define R_SERIAL1_CTRL__tr_par__BITNR 10
#define R_SERIAL1_CTRL__tr_par__WIDTH 1
#define R_SERIAL1_CTRL__tr_par__even 0
#define R_SERIAL1_CTRL__tr_par__odd 1
#define R_SERIAL1_CTRL__tr_par_en__BITNR 9
#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1
#define R_SERIAL1_CTRL__tr_par_en__disable 0
#define R_SERIAL1_CTRL__tr_par_en__enable 1
#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1
#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0
#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1
#define R_SERIAL1_CTRL__data_out__BITNR 0
#define R_SERIAL1_CTRL__data_out__WIDTH 8

#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b)
#define R_SERIAL1_BAUD__tr_baud__BITNR 4
#define R_SERIAL1_BAUD__tr_baud__WIDTH 4
#define R_SERIAL1_BAUD__tr_baud__c300Hz 0
#define R_SERIAL1_BAUD__tr_baud__c600Hz 1
#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2
#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3
#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4
#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5
#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6
#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7
#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8
#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9
#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10
#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11
#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12
#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13
#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14
#define R_SERIAL1_BAUD__tr_baud__reserved 15
#define R_SERIAL1_BAUD__rec_baud__BITNR 0
#define R_SERIAL1_BAUD__rec_baud__WIDTH 4
#define R_SERIAL1_BAUD__rec_baud__c300Hz 0
#define R_SERIAL1_BAUD__rec_baud__c600Hz 1
#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2
#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3
#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4
#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5
#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6
#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7
#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8
#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9
#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10
#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11
#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12
#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13
#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14
#define R_SERIAL1_BAUD__rec_baud__reserved 15

#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a)
#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1
#define R_SERIAL1_REC_CTRL__dma_err__stop 0
#define R_SERIAL1_REC_CTRL__dma_err__ignore 1
#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1
#define R_SERIAL1_REC_CTRL__rec_enable__disable 0
#define R_SERIAL1_REC_CTRL__rec_enable__enable 1
#define R_SERIAL1_REC_CTRL__rts___BITNR 5
#define R_SERIAL1_REC_CTRL__rts___WIDTH 1
#define R_SERIAL1_REC_CTRL__rts___active 0
#define R_SERIAL1_REC_CTRL__rts___inactive 1
#define R_SERIAL1_REC_CTRL__sampling__BITNR 4
#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1
#define R_SERIAL1_REC_CTRL__sampling__middle 0
#define R_SERIAL1_REC_CTRL__sampling__majority 1
#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1
#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0
#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1
#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1
#define R_SERIAL1_REC_CTRL__rec_par__even 0
#define R_SERIAL1_REC_CTRL__rec_par__odd 1
#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1
#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0
#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1
#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1
#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0
#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1

#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069)
#define R_SERIAL1_TR_CTRL__txd__BITNR 7
#define R_SERIAL1_TR_CTRL__txd__WIDTH 1
#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1
#define R_SERIAL1_TR_CTRL__tr_enable__disable 0
#define R_SERIAL1_TR_CTRL__tr_enable__enable 1
#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1
#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0
#define R_SERIAL1_TR_CTRL__auto_cts__active 1
#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1
#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0
#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1
#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1
#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0
#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1
#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1
#define R_SERIAL1_TR_CTRL__tr_par__even 0
#define R_SERIAL1_TR_CTRL__tr_par__odd 1
#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1
#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0
#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1
#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1
#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0
#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1

#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068)
#define R_SERIAL1_TR_DATA__data_out__BITNR 0
#define R_SERIAL1_TR_DATA__data_out__WIDTH 8

#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068)
#define R_SERIAL1_READ__xoff_detect__BITNR 15
#define R_SERIAL1_READ__xoff_detect__WIDTH 1
#define R_SERIAL1_READ__xoff_detect__no_xoff 0
#define R_SERIAL1_READ__xoff_detect__xoff 1
#define R_SERIAL1_READ__cts___BITNR 14
#define R_SERIAL1_READ__cts___WIDTH 1
#define R_SERIAL1_READ__cts___active 0
#define R_SERIAL1_READ__cts___inactive 1
#define R_SERIAL1_READ__tr_ready__BITNR 13
#define R_SERIAL1_READ__tr_ready__WIDTH 1
#define R_SERIAL1_READ__tr_ready__full 0
#define R_SERIAL1_READ__tr_ready__ready 1
#define R_SERIAL1_READ__rxd__BITNR 12
#define R_SERIAL1_READ__rxd__WIDTH 1
#define R_SERIAL1_READ__overrun__BITNR 11
#define R_SERIAL1_READ__overrun__WIDTH 1
#define R_SERIAL1_READ__overrun__no 0
#define R_SERIAL1_READ__overrun__yes 1
#define R_SERIAL1_READ__par_err__BITNR 10
#define R_SERIAL1_READ__par_err__WIDTH 1
#define R_SERIAL1_READ__par_err__no 0
#define R_SERIAL1_READ__par_err__yes 1
#define R_SERIAL1_READ__framing_err__BITNR 9
#define R_SERIAL1_READ__framing_err__WIDTH 1
#define R_SERIAL1_READ__framing_err__no 0
#define R_SERIAL1_READ__framing_err__yes 1
#define R_SERIAL1_READ__data_avail__BITNR 8
#define R_SERIAL1_READ__data_avail__WIDTH 1
#define R_SERIAL1_READ__data_avail__no 0
#define R_SERIAL1_READ__data_avail__yes 1
#define R_SERIAL1_READ__data_in__BITNR 0
#define R_SERIAL1_READ__data_in__WIDTH 8

#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069)
#define R_SERIAL1_STATUS__xoff_detect__BITNR 7
#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1
#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0
#define R_SERIAL1_STATUS__xoff_detect__xoff 1
#define R_SERIAL1_STATUS__cts___BITNR 6
#define R_SERIAL1_STATUS__cts___WIDTH 1
#define R_SERIAL1_STATUS__cts___active 0
#define R_SERIAL1_STATUS__cts___inactive 1
#define R_SERIAL1_STATUS__tr_ready__BITNR 5
#define R_SERIAL1_STATUS__tr_ready__WIDTH 1
#define R_SERIAL1_STATUS__tr_ready__full 0
#define R_SERIAL1_STATUS__tr_ready__ready 1
#define R_SERIAL1_STATUS__rxd__BITNR 4
#define R_SERIAL1_STATUS__rxd__WIDTH 1
#define R_SERIAL1_STATUS__overrun__BITNR 3
#define R_SERIAL1_STATUS__overrun__WIDTH 1
#define R_SERIAL1_STATUS__overrun__no 0
#define R_SERIAL1_STATUS__overrun__yes 1
#define R_SERIAL1_STATUS__par_err__BITNR