sv_addr.agh

linux-2.6.15.6

#define R_PORT_PB_DATA__data_out__BITNR 0
#define R_PORT_PB_DATA__data_out__WIDTH 8

#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039)
#define R_PORT_PB_DIR__dir7__BITNR 7
#define R_PORT_PB_DIR__dir7__WIDTH 1
#define R_PORT_PB_DIR__dir7__input 0
#define R_PORT_PB_DIR__dir7__output 1
#define R_PORT_PB_DIR__dir6__BITNR 6
#define R_PORT_PB_DIR__dir6__WIDTH 1
#define R_PORT_PB_DIR__dir6__input 0
#define R_PORT_PB_DIR__dir6__output 1
#define R_PORT_PB_DIR__dir5__BITNR 5
#define R_PORT_PB_DIR__dir5__WIDTH 1
#define R_PORT_PB_DIR__dir5__input 0
#define R_PORT_PB_DIR__dir5__output 1
#define R_PORT_PB_DIR__dir4__BITNR 4
#define R_PORT_PB_DIR__dir4__WIDTH 1
#define R_PORT_PB_DIR__dir4__input 0
#define R_PORT_PB_DIR__dir4__output 1
#define R_PORT_PB_DIR__dir3__BITNR 3
#define R_PORT_PB_DIR__dir3__WIDTH 1
#define R_PORT_PB_DIR__dir3__input 0
#define R_PORT_PB_DIR__dir3__output 1
#define R_PORT_PB_DIR__dir2__BITNR 2
#define R_PORT_PB_DIR__dir2__WIDTH 1
#define R_PORT_PB_DIR__dir2__input 0
#define R_PORT_PB_DIR__dir2__output 1
#define R_PORT_PB_DIR__dir1__BITNR 1
#define R_PORT_PB_DIR__dir1__WIDTH 1
#define R_PORT_PB_DIR__dir1__input 0
#define R_PORT_PB_DIR__dir1__output 1
#define R_PORT_PB_DIR__dir0__BITNR 0
#define R_PORT_PB_DIR__dir0__WIDTH 1
#define R_PORT_PB_DIR__dir0__input 0
#define R_PORT_PB_DIR__dir0__output 1

#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a)
#define R_PORT_PB_CONFIG__cs7__BITNR 7
#define R_PORT_PB_CONFIG__cs7__WIDTH 1
#define R_PORT_PB_CONFIG__cs7__port 0
#define R_PORT_PB_CONFIG__cs7__cs 1
#define R_PORT_PB_CONFIG__cs6__BITNR 6
#define R_PORT_PB_CONFIG__cs6__WIDTH 1
#define R_PORT_PB_CONFIG__cs6__port 0
#define R_PORT_PB_CONFIG__cs6__cs 1
#define R_PORT_PB_CONFIG__cs5__BITNR 5
#define R_PORT_PB_CONFIG__cs5__WIDTH 1
#define R_PORT_PB_CONFIG__cs5__port 0
#define R_PORT_PB_CONFIG__cs5__cs 1
#define R_PORT_PB_CONFIG__cs4__BITNR 4
#define R_PORT_PB_CONFIG__cs4__WIDTH 1
#define R_PORT_PB_CONFIG__cs4__port 0
#define R_PORT_PB_CONFIG__cs4__cs 1
#define R_PORT_PB_CONFIG__cs3__BITNR 3
#define R_PORT_PB_CONFIG__cs3__WIDTH 1
#define R_PORT_PB_CONFIG__cs3__port 0
#define R_PORT_PB_CONFIG__cs3__cs 1
#define R_PORT_PB_CONFIG__cs2__BITNR 2
#define R_PORT_PB_CONFIG__cs2__WIDTH 1
#define R_PORT_PB_CONFIG__cs2__port 0
#define R_PORT_PB_CONFIG__cs2__cs 1
#define R_PORT_PB_CONFIG__scsi1__BITNR 1
#define R_PORT_PB_CONFIG__scsi1__WIDTH 1
#define R_PORT_PB_CONFIG__scsi1__port_cs 0
#define R_PORT_PB_CONFIG__scsi1__enph 1
#define R_PORT_PB_CONFIG__scsi0__BITNR 0
#define R_PORT_PB_CONFIG__scsi0__WIDTH 1
#define R_PORT_PB_CONFIG__scsi0__port_cs 0
#define R_PORT_PB_CONFIG__scsi0__enph 1

#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b)
#define R_PORT_PB_I2C__syncser3__BITNR 5
#define R_PORT_PB_I2C__syncser3__WIDTH 1
#define R_PORT_PB_I2C__syncser3__port_cs 0
#define R_PORT_PB_I2C__syncser3__ss3extra 1
#define R_PORT_PB_I2C__syncser1__BITNR 4
#define R_PORT_PB_I2C__syncser1__WIDTH 1
#define R_PORT_PB_I2C__syncser1__port_cs 0
#define R_PORT_PB_I2C__syncser1__ss1extra 1
#define R_PORT_PB_I2C__i2c_en__BITNR 3
#define R_PORT_PB_I2C__i2c_en__WIDTH 1
#define R_PORT_PB_I2C__i2c_en__off 0
#define R_PORT_PB_I2C__i2c_en__on 1
#define R_PORT_PB_I2C__i2c_d__BITNR 2
#define R_PORT_PB_I2C__i2c_d__WIDTH 1
#define R_PORT_PB_I2C__i2c_clk__BITNR 1
#define R_PORT_PB_I2C__i2c_clk__WIDTH 1
#define R_PORT_PB_I2C__i2c_oe___BITNR 0
#define R_PORT_PB_I2C__i2c_oe___WIDTH 1
#define R_PORT_PB_I2C__i2c_oe___enable 0
#define R_PORT_PB_I2C__i2c_oe___disable 1

#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038)
#define R_PORT_PB_READ__data_in__BITNR 0
#define R_PORT_PB_READ__data_in__WIDTH 8

/*
!* Serial port registers
!*/

#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060)
#define R_SERIAL0_CTRL__tr_baud__BITNR 28
#define R_SERIAL0_CTRL__tr_baud__WIDTH 4
#define R_SERIAL0_CTRL__tr_baud__c300Hz 0
#define R_SERIAL0_CTRL__tr_baud__c600Hz 1
#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2
#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3
#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4
#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5
#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6
#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7
#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8
#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9
#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10
#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11
#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12
#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13
#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14
#define R_SERIAL0_CTRL__tr_baud__reserved 15
#define R_SERIAL0_CTRL__rec_baud__BITNR 24
#define R_SERIAL0_CTRL__rec_baud__WIDTH 4
#define R_SERIAL0_CTRL__rec_baud__c300Hz 0
#define R_SERIAL0_CTRL__rec_baud__c600Hz 1
#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2
#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3
#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4
#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5
#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6
#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7
#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8
#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9
#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10
#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11
#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12
#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13
#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14
#define R_SERIAL0_CTRL__rec_baud__reserved 15
#define R_SERIAL0_CTRL__dma_err__BITNR 23
#define R_SERIAL0_CTRL__dma_err__WIDTH 1
#define R_SERIAL0_CTRL__dma_err__stop 0
#define R_SERIAL0_CTRL__dma_err__ignore 1
#define R_SERIAL0_CTRL__rec_enable__BITNR 22
#define R_SERIAL0_CTRL__rec_enable__WIDTH 1
#define R_SERIAL0_CTRL__rec_enable__disable 0
#define R_SERIAL0_CTRL__rec_enable__enable 1
#define R_SERIAL0_CTRL__rts___BITNR 21
#define R_SERIAL0_CTRL__rts___WIDTH 1
#define R_SERIAL0_CTRL__rts___active 0
#define R_SERIAL0_CTRL__rts___inactive 1
#define R_SERIAL0_CTRL__sampling__BITNR 20
#define R_SERIAL0_CTRL__sampling__WIDTH 1
#define R_SERIAL0_CTRL__sampling__middle 0
#define R_SERIAL0_CTRL__sampling__majority 1
#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1
#define R_SERIAL0_CTRL__rec_stick_par__normal 0
#define R_SERIAL0_CTRL__rec_stick_par__stick 1
#define R_SERIAL0_CTRL__rec_par__BITNR 18
#define R_SERIAL0_CTRL__rec_par__WIDTH 1
#define R_SERIAL0_CTRL__rec_par__even 0
#define R_SERIAL0_CTRL__rec_par__odd 1
#define R_SERIAL0_CTRL__rec_par_en__BITNR 17
#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1
#define R_SERIAL0_CTRL__rec_par_en__disable 0
#define R_SERIAL0_CTRL__rec_par_en__enable 1
#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1
#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0
#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1
#define R_SERIAL0_CTRL__txd__BITNR 15
#define R_SERIAL0_CTRL__txd__WIDTH 1
#define R_SERIAL0_CTRL__tr_enable__BITNR 14
#define R_SERIAL0_CTRL__tr_enable__WIDTH 1
#define R_SERIAL0_CTRL__tr_enable__disable 0
#define R_SERIAL0_CTRL__tr_enable__enable 1
#define R_SERIAL0_CTRL__auto_cts__BITNR 13
#define R_SERIAL0_CTRL__auto_cts__WIDTH 1
#define R_SERIAL0_CTRL__auto_cts__disabled 0
#define R_SERIAL0_CTRL__auto_cts__active 1
#define R_SERIAL0_CTRL__stop_bits__BITNR 12
#define R_SERIAL0_CTRL__stop_bits__WIDTH 1
#define R_SERIAL0_CTRL__stop_bits__one_bit 0
#define R_SERIAL0_CTRL__stop_bits__two_bits 1
#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1
#define R_SERIAL0_CTRL__tr_stick_par__normal 0
#define R_SERIAL0_CTRL__tr_stick_par__stick 1
#define R_SERIAL0_CTRL__tr_par__BITNR 10
#define R_SERIAL0_CTRL__tr_par__WIDTH 1
#define R_SERIAL0_CTRL__tr_par__even 0
#define R_SERIAL0_CTRL__tr_par__odd 1
#define R_SERIAL0_CTRL__tr_par_en__BITNR 9
#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1
#define R_SERIAL0_CTRL__tr_par_en__disable 0
#define R_SERIAL0_CTRL__tr_par_en__enable 1
#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1
#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0
#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1
#define R_SERIAL0_CTRL__data_out__BITNR 0
#define R_SERIAL0_CTRL__data_out__WIDTH 8

#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063)
#define R_SERIAL0_BAUD__tr_baud__BITNR 4
#define R_SERIAL0_BAUD__tr_baud__WIDTH 4
#define R_SERIAL0_BAUD__tr_baud__c300Hz 0
#define R_SERIAL0_BAUD__tr_baud__c600Hz 1
#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2
#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3
#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4
#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5
#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6
#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7
#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8
#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9
#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10
#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11
#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12
#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13
#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14
#define R_SERIAL0_BAUD__tr_baud__reserved 15
#define R_SERIAL0_BAUD__rec_baud__BITNR 0
#define R_SERIAL0_BAUD__rec_baud__WIDTH 4
#define R_SERIAL0_BAUD__rec_baud__c300Hz 0
#define R_SERIAL0_BAUD__rec_baud__c600Hz 1
#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2
#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3
#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4
#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5
#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6
#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7
#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8
#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9
#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10
#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11
#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12
#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13
#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14
#define R_SERIAL0_BAUD__rec_baud__reserved 15

#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062)
#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1
#define R_SERIAL0_REC_CTRL__dma_err__stop 0
#define R_SERIAL0_REC_CTRL__dma_err__ignore 1
#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1
#define R_SERIAL0_REC_CTRL__rec_enable__disable 0
#define R_SERIAL0_REC_CTRL__rec_enable__enable 1
#define R_SERIAL0_REC_CTRL__rts___BITNR 5
#define R_SERIAL0_REC_CTRL__rts___WIDTH 1
#define R_SERIAL0_REC_CTRL__rts___active 0
#define R_SERIAL0_REC_CTRL__rts___inactive 1
#define R_SERIAL0_REC_CTRL__sampling__BITNR 4
#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1
#define R_SERIAL0_REC_CTRL__sampling__middle 0
#define R_SERIAL0_REC_CTRL__sampling__majority 1
#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1
#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0
#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1
#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1
#define R_SERIAL0_REC_CTRL__rec_par__even 0
#define R_SERIAL0_REC_CTRL__rec_par__odd 1
#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1
#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0
#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1
#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1
#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0
#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1

#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061)
#define R_SERIAL0_TR_CTRL__txd__BITNR 7
#define R_SERIAL0_TR_CTRL__txd__WIDTH 1
#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1
#define R_SERIAL0_TR_CTRL__tr_enable__disable 0
#define R_SERIAL0_TR_CTRL__tr_enable__enable 1
#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1
#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0
#define R_SERIAL0_TR_CTRL__auto_cts__active 1
#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1
#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0
#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1
#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1
#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0
#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1
#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1
#define R_SERIAL0_TR_CTRL__tr_par__even 0
#define R_SERIAL0_TR_CTRL__tr_par__odd 1
#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1
#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0
#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1
#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1
#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0
#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1

#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060)
#define R_SERIAL0_TR_DATA__data_out__BITNR 0
#define R_SERIAL0_TR_DATA__data_out__WIDTH 8

#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060)
#define R_SERIAL0_READ__xoff_detect__BITNR 15
#define R_SERIAL0_READ__xoff_detect__WIDTH 1
#define R_SERIAL0_READ__xoff_detect__no_xoff 0
#define R_SERIAL0_READ__xoff_detect__xoff 1
#define R_SERIAL0_READ__cts___BITNR 14
#define R_SERIAL0_READ__cts___WIDTH 1
#define R_SERIAL0_READ__cts___active 0
#define R_SERIAL0_READ__cts___inactive 1
#define R_SERIAL0_READ__tr_ready__BITNR 13
#define R_SERIAL0_READ__tr_ready__WIDTH 1
#define R_SERIAL0_READ__tr_ready__full 0
#define R_SERIAL0_READ__tr_ready__ready 1
#define R_SERIAL0_READ__rxd__BITNR 12
#define R_SERIAL0_READ__rxd__WIDTH 1
#define R_SERIAL0_READ__overrun__BITNR 11
#define R_SERIAL0_READ__overrun__WIDTH 1
#define R_SERIAL0_READ__overrun__no 0