sv_addr.agh

linux-2.6.15.6

#define R_SHARED_RAM_CONFIG__enable__no 0
#define R_SHARED_RAM_CONFIG__pint__BITNR 1
#define R_SHARED_RAM_CONFIG__pint__WIDTH 1
#define R_SHARED_RAM_CONFIG__pint__int 1
#define R_SHARED_RAM_CONFIG__pint__nop 0
#define R_SHARED_RAM_CONFIG__clri__BITNR 0
#define R_SHARED_RAM_CONFIG__clri__WIDTH 1
#define R_SHARED_RAM_CONFIG__clri__clr 1
#define R_SHARED_RAM_CONFIG__clri__nop 0

#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044)
#define R_SHARED_RAM_ADDR__base_addr__BITNR 8
#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22

/*
!* General config registers
!*/

#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c)
#define R_GEN_CONFIG__par_w__BITNR 31
#define R_GEN_CONFIG__par_w__WIDTH 1
#define R_GEN_CONFIG__par_w__select 1
#define R_GEN_CONFIG__par_w__disable 0
#define R_GEN_CONFIG__usb2__BITNR 30
#define R_GEN_CONFIG__usb2__WIDTH 1
#define R_GEN_CONFIG__usb2__select 1
#define R_GEN_CONFIG__usb2__disable 0
#define R_GEN_CONFIG__usb1__BITNR 29
#define R_GEN_CONFIG__usb1__WIDTH 1
#define R_GEN_CONFIG__usb1__select 1
#define R_GEN_CONFIG__usb1__disable 0
#define R_GEN_CONFIG__g24dir__BITNR 27
#define R_GEN_CONFIG__g24dir__WIDTH 1
#define R_GEN_CONFIG__g24dir__in 0
#define R_GEN_CONFIG__g24dir__out 1
#define R_GEN_CONFIG__g16_23dir__BITNR 26
#define R_GEN_CONFIG__g16_23dir__WIDTH 1
#define R_GEN_CONFIG__g16_23dir__in 0
#define R_GEN_CONFIG__g16_23dir__out 1
#define R_GEN_CONFIG__g8_15dir__BITNR 25
#define R_GEN_CONFIG__g8_15dir__WIDTH 1
#define R_GEN_CONFIG__g8_15dir__in 0
#define R_GEN_CONFIG__g8_15dir__out 1
#define R_GEN_CONFIG__g0dir__BITNR 24
#define R_GEN_CONFIG__g0dir__WIDTH 1
#define R_GEN_CONFIG__g0dir__in 0
#define R_GEN_CONFIG__g0dir__out 1
#define R_GEN_CONFIG__dma9__BITNR 23
#define R_GEN_CONFIG__dma9__WIDTH 1
#define R_GEN_CONFIG__dma9__usb 0
#define R_GEN_CONFIG__dma9__serial1 1
#define R_GEN_CONFIG__dma8__BITNR 22
#define R_GEN_CONFIG__dma8__WIDTH 1
#define R_GEN_CONFIG__dma8__usb 0
#define R_GEN_CONFIG__dma8__serial1 1
#define R_GEN_CONFIG__dma7__BITNR 20
#define R_GEN_CONFIG__dma7__WIDTH 2
#define R_GEN_CONFIG__dma7__unused 0
#define R_GEN_CONFIG__dma7__serial0 1
#define R_GEN_CONFIG__dma7__extdma1 2
#define R_GEN_CONFIG__dma7__intdma6 3
#define R_GEN_CONFIG__dma6__BITNR 18
#define R_GEN_CONFIG__dma6__WIDTH 2
#define R_GEN_CONFIG__dma6__unused 0
#define R_GEN_CONFIG__dma6__serial0 1
#define R_GEN_CONFIG__dma6__extdma1 2
#define R_GEN_CONFIG__dma6__intdma7 3
#define R_GEN_CONFIG__dma5__BITNR 16
#define R_GEN_CONFIG__dma5__WIDTH 2
#define R_GEN_CONFIG__dma5__par1 0
#define R_GEN_CONFIG__dma5__scsi1 1
#define R_GEN_CONFIG__dma5__serial3 2
#define R_GEN_CONFIG__dma5__extdma0 3
#define R_GEN_CONFIG__dma4__BITNR 14
#define R_GEN_CONFIG__dma4__WIDTH 2
#define R_GEN_CONFIG__dma4__par1 0
#define R_GEN_CONFIG__dma4__scsi1 1
#define R_GEN_CONFIG__dma4__serial3 2
#define R_GEN_CONFIG__dma4__extdma0 3
#define R_GEN_CONFIG__dma3__BITNR 12
#define R_GEN_CONFIG__dma3__WIDTH 2
#define R_GEN_CONFIG__dma3__par0 0
#define R_GEN_CONFIG__dma3__scsi0 1
#define R_GEN_CONFIG__dma3__serial2 2
#define R_GEN_CONFIG__dma3__ata 3
#define R_GEN_CONFIG__dma2__BITNR 10
#define R_GEN_CONFIG__dma2__WIDTH 2
#define R_GEN_CONFIG__dma2__par0 0
#define R_GEN_CONFIG__dma2__scsi0 1
#define R_GEN_CONFIG__dma2__serial2 2
#define R_GEN_CONFIG__dma2__ata 3
#define R_GEN_CONFIG__mio_w__BITNR 9
#define R_GEN_CONFIG__mio_w__WIDTH 1
#define R_GEN_CONFIG__mio_w__select 1
#define R_GEN_CONFIG__mio_w__disable 0
#define R_GEN_CONFIG__ser3__BITNR 8
#define R_GEN_CONFIG__ser3__WIDTH 1
#define R_GEN_CONFIG__ser3__select 1
#define R_GEN_CONFIG__ser3__disable 0
#define R_GEN_CONFIG__par1__BITNR 7
#define R_GEN_CONFIG__par1__WIDTH 1
#define R_GEN_CONFIG__par1__select 1
#define R_GEN_CONFIG__par1__disable 0
#define R_GEN_CONFIG__scsi0w__BITNR 6
#define R_GEN_CONFIG__scsi0w__WIDTH 1
#define R_GEN_CONFIG__scsi0w__select 1
#define R_GEN_CONFIG__scsi0w__disable 0
#define R_GEN_CONFIG__scsi1__BITNR 5
#define R_GEN_CONFIG__scsi1__WIDTH 1
#define R_GEN_CONFIG__scsi1__select 1
#define R_GEN_CONFIG__scsi1__disable 0
#define R_GEN_CONFIG__mio__BITNR 4
#define R_GEN_CONFIG__mio__WIDTH 1
#define R_GEN_CONFIG__mio__select 1
#define R_GEN_CONFIG__mio__disable 0
#define R_GEN_CONFIG__ser2__BITNR 3
#define R_GEN_CONFIG__ser2__WIDTH 1
#define R_GEN_CONFIG__ser2__select 1
#define R_GEN_CONFIG__ser2__disable 0
#define R_GEN_CONFIG__par0__BITNR 2
#define R_GEN_CONFIG__par0__WIDTH 1
#define R_GEN_CONFIG__par0__select 1
#define R_GEN_CONFIG__par0__disable 0
#define R_GEN_CONFIG__ata__BITNR 1
#define R_GEN_CONFIG__ata__WIDTH 1
#define R_GEN_CONFIG__ata__select 1
#define R_GEN_CONFIG__ata__disable 0
#define R_GEN_CONFIG__scsi0__BITNR 0
#define R_GEN_CONFIG__scsi0__WIDTH 1
#define R_GEN_CONFIG__scsi0__select 1
#define R_GEN_CONFIG__scsi0__disable 0

#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034)
#define R_GEN_CONFIG_II__sermode3__BITNR 6
#define R_GEN_CONFIG_II__sermode3__WIDTH 1
#define R_GEN_CONFIG_II__sermode3__async 0
#define R_GEN_CONFIG_II__sermode3__sync 1
#define R_GEN_CONFIG_II__sermode1__BITNR 4
#define R_GEN_CONFIG_II__sermode1__WIDTH 1
#define R_GEN_CONFIG_II__sermode1__async 0
#define R_GEN_CONFIG_II__sermode1__sync 1
#define R_GEN_CONFIG_II__ext_clk__BITNR 2
#define R_GEN_CONFIG_II__ext_clk__WIDTH 1
#define R_GEN_CONFIG_II__ext_clk__select 1
#define R_GEN_CONFIG_II__ext_clk__disable 0
#define R_GEN_CONFIG_II__ser2__BITNR 1
#define R_GEN_CONFIG_II__ser2__WIDTH 1
#define R_GEN_CONFIG_II__ser2__select 1
#define R_GEN_CONFIG_II__ser2__disable 0
#define R_GEN_CONFIG_II__ser3__BITNR 0
#define R_GEN_CONFIG_II__ser3__WIDTH 1
#define R_GEN_CONFIG_II__ser3__select 1
#define R_GEN_CONFIG_II__ser3__disable 0

#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028)
#define R_PORT_G_DATA__data__BITNR 0
#define R_PORT_G_DATA__data__WIDTH 32

/*
!* General port configuration registers
!*/

#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030)
#define R_PORT_PA_SET__dir7__BITNR 15
#define R_PORT_PA_SET__dir7__WIDTH 1
#define R_PORT_PA_SET__dir7__input 0
#define R_PORT_PA_SET__dir7__output 1
#define R_PORT_PA_SET__dir6__BITNR 14
#define R_PORT_PA_SET__dir6__WIDTH 1
#define R_PORT_PA_SET__dir6__input 0
#define R_PORT_PA_SET__dir6__output 1
#define R_PORT_PA_SET__dir5__BITNR 13
#define R_PORT_PA_SET__dir5__WIDTH 1
#define R_PORT_PA_SET__dir5__input 0
#define R_PORT_PA_SET__dir5__output 1
#define R_PORT_PA_SET__dir4__BITNR 12
#define R_PORT_PA_SET__dir4__WIDTH 1
#define R_PORT_PA_SET__dir4__input 0
#define R_PORT_PA_SET__dir4__output 1
#define R_PORT_PA_SET__dir3__BITNR 11
#define R_PORT_PA_SET__dir3__WIDTH 1
#define R_PORT_PA_SET__dir3__input 0
#define R_PORT_PA_SET__dir3__output 1
#define R_PORT_PA_SET__dir2__BITNR 10
#define R_PORT_PA_SET__dir2__WIDTH 1
#define R_PORT_PA_SET__dir2__input 0
#define R_PORT_PA_SET__dir2__output 1
#define R_PORT_PA_SET__dir1__BITNR 9
#define R_PORT_PA_SET__dir1__WIDTH 1
#define R_PORT_PA_SET__dir1__input 0
#define R_PORT_PA_SET__dir1__output 1
#define R_PORT_PA_SET__dir0__BITNR 8
#define R_PORT_PA_SET__dir0__WIDTH 1
#define R_PORT_PA_SET__dir0__input 0
#define R_PORT_PA_SET__dir0__output 1
#define R_PORT_PA_SET__data_out__BITNR 0
#define R_PORT_PA_SET__data_out__WIDTH 8

#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030)
#define R_PORT_PA_DATA__data_out__BITNR 0
#define R_PORT_PA_DATA__data_out__WIDTH 8

#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031)
#define R_PORT_PA_DIR__dir7__BITNR 7
#define R_PORT_PA_DIR__dir7__WIDTH 1
#define R_PORT_PA_DIR__dir7__input 0
#define R_PORT_PA_DIR__dir7__output 1
#define R_PORT_PA_DIR__dir6__BITNR 6
#define R_PORT_PA_DIR__dir6__WIDTH 1
#define R_PORT_PA_DIR__dir6__input 0
#define R_PORT_PA_DIR__dir6__output 1
#define R_PORT_PA_DIR__dir5__BITNR 5
#define R_PORT_PA_DIR__dir5__WIDTH 1
#define R_PORT_PA_DIR__dir5__input 0
#define R_PORT_PA_DIR__dir5__output 1
#define R_PORT_PA_DIR__dir4__BITNR 4
#define R_PORT_PA_DIR__dir4__WIDTH 1
#define R_PORT_PA_DIR__dir4__input 0
#define R_PORT_PA_DIR__dir4__output 1
#define R_PORT_PA_DIR__dir3__BITNR 3
#define R_PORT_PA_DIR__dir3__WIDTH 1
#define R_PORT_PA_DIR__dir3__input 0
#define R_PORT_PA_DIR__dir3__output 1
#define R_PORT_PA_DIR__dir2__BITNR 2
#define R_PORT_PA_DIR__dir2__WIDTH 1
#define R_PORT_PA_DIR__dir2__input 0
#define R_PORT_PA_DIR__dir2__output 1
#define R_PORT_PA_DIR__dir1__BITNR 1
#define R_PORT_PA_DIR__dir1__WIDTH 1
#define R_PORT_PA_DIR__dir1__input 0
#define R_PORT_PA_DIR__dir1__output 1
#define R_PORT_PA_DIR__dir0__BITNR 0
#define R_PORT_PA_DIR__dir0__WIDTH 1
#define R_PORT_PA_DIR__dir0__input 0
#define R_PORT_PA_DIR__dir0__output 1

#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030)
#define R_PORT_PA_READ__data_in__BITNR 0
#define R_PORT_PA_READ__data_in__WIDTH 8

#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038)
#define R_PORT_PB_SET__syncser3__BITNR 29
#define R_PORT_PB_SET__syncser3__WIDTH 1
#define R_PORT_PB_SET__syncser3__port_cs 0
#define R_PORT_PB_SET__syncser3__ss3extra 1
#define R_PORT_PB_SET__syncser1__BITNR 28
#define R_PORT_PB_SET__syncser1__WIDTH 1
#define R_PORT_PB_SET__syncser1__port_cs 0
#define R_PORT_PB_SET__syncser1__ss1extra 1
#define R_PORT_PB_SET__i2c_en__BITNR 27
#define R_PORT_PB_SET__i2c_en__WIDTH 1
#define R_PORT_PB_SET__i2c_en__off 0
#define R_PORT_PB_SET__i2c_en__on 1
#define R_PORT_PB_SET__i2c_d__BITNR 26
#define R_PORT_PB_SET__i2c_d__WIDTH 1
#define R_PORT_PB_SET__i2c_clk__BITNR 25
#define R_PORT_PB_SET__i2c_clk__WIDTH 1
#define R_PORT_PB_SET__i2c_oe___BITNR 24
#define R_PORT_PB_SET__i2c_oe___WIDTH 1
#define R_PORT_PB_SET__i2c_oe___enable 0
#define R_PORT_PB_SET__i2c_oe___disable 1
#define R_PORT_PB_SET__cs7__BITNR 23
#define R_PORT_PB_SET__cs7__WIDTH 1
#define R_PORT_PB_SET__cs7__port 0
#define R_PORT_PB_SET__cs7__cs 1
#define R_PORT_PB_SET__cs6__BITNR 22
#define R_PORT_PB_SET__cs6__WIDTH 1
#define R_PORT_PB_SET__cs6__port 0
#define R_PORT_PB_SET__cs6__cs 1
#define R_PORT_PB_SET__cs5__BITNR 21
#define R_PORT_PB_SET__cs5__WIDTH 1
#define R_PORT_PB_SET__cs5__port 0
#define R_PORT_PB_SET__cs5__cs 1
#define R_PORT_PB_SET__cs4__BITNR 20
#define R_PORT_PB_SET__cs4__WIDTH 1
#define R_PORT_PB_SET__cs4__port 0
#define R_PORT_PB_SET__cs4__cs 1
#define R_PORT_PB_SET__cs3__BITNR 19
#define R_PORT_PB_SET__cs3__WIDTH 1
#define R_PORT_PB_SET__cs3__port 0
#define R_PORT_PB_SET__cs3__cs 1
#define R_PORT_PB_SET__cs2__BITNR 18
#define R_PORT_PB_SET__cs2__WIDTH 1
#define R_PORT_PB_SET__cs2__port 0
#define R_PORT_PB_SET__cs2__cs 1
#define R_PORT_PB_SET__scsi1__BITNR 17
#define R_PORT_PB_SET__scsi1__WIDTH 1
#define R_PORT_PB_SET__scsi1__port_cs 0
#define R_PORT_PB_SET__scsi1__enph 1
#define R_PORT_PB_SET__scsi0__BITNR 16
#define R_PORT_PB_SET__scsi0__WIDTH 1
#define R_PORT_PB_SET__scsi0__port_cs 0
#define R_PORT_PB_SET__scsi0__enph 1
#define R_PORT_PB_SET__dir7__BITNR 15
#define R_PORT_PB_SET__dir7__WIDTH 1
#define R_PORT_PB_SET__dir7__input 0
#define R_PORT_PB_SET__dir7__output 1
#define R_PORT_PB_SET__dir6__BITNR 14
#define R_PORT_PB_SET__dir6__WIDTH 1
#define R_PORT_PB_SET__dir6__input 0
#define R_PORT_PB_SET__dir6__output 1
#define R_PORT_PB_SET__dir5__BITNR 13
#define R_PORT_PB_SET__dir5__WIDTH 1
#define R_PORT_PB_SET__dir5__input 0
#define R_PORT_PB_SET__dir5__output 1
#define R_PORT_PB_SET__dir4__BITNR 12
#define R_PORT_PB_SET__dir4__WIDTH 1
#define R_PORT_PB_SET__dir4__input 0
#define R_PORT_PB_SET__dir4__output 1
#define R_PORT_PB_SET__dir3__BITNR 11
#define R_PORT_PB_SET__dir3__WIDTH 1
#define R_PORT_PB_SET__dir3__input 0
#define R_PORT_PB_SET__dir3__output 1
#define R_PORT_PB_SET__dir2__BITNR 10
#define R_PORT_PB_SET__dir2__WIDTH 1
#define R_PORT_PB_SET__dir2__input 0
#define R_PORT_PB_SET__dir2__output 1
#define R_PORT_PB_SET__dir1__BITNR 9
#define R_PORT_PB_SET__dir1__WIDTH 1
#define R_PORT_PB_SET__dir1__input 0
#define R_PORT_PB_SET__dir1__output 1
#define R_PORT_PB_SET__dir0__BITNR 8
#define R_PORT_PB_SET__dir0__WIDTH 1
#define R_PORT_PB_SET__dir0__input 0
#define R_PORT_PB_SET__dir0__output 1
#define R_PORT_PB_SET__data_out__BITNR 0
#define R_PORT_PB_SET__data_out__WIDTH 8

#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038)