sv_addr.agh

linux-2.6.15.6

#define R_SDRAM_CONFIG__group_sel__bit26 26
#define R_SDRAM_CONFIG__group_sel__bit27 27
#define R_SDRAM_CONFIG__group_sel__bit28 28
#define R_SDRAM_CONFIG__group_sel__bit29 29
#define R_SDRAM_CONFIG__ca1__BITNR 13
#define R_SDRAM_CONFIG__ca1__WIDTH 3
#define R_SDRAM_CONFIG__bank_sel1__BITNR 8
#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5
#define R_SDRAM_CONFIG__bank_sel1__bit9 9
#define R_SDRAM_CONFIG__bank_sel1__bit10 10
#define R_SDRAM_CONFIG__bank_sel1__bit11 11
#define R_SDRAM_CONFIG__bank_sel1__bit12 12
#define R_SDRAM_CONFIG__bank_sel1__bit13 13
#define R_SDRAM_CONFIG__bank_sel1__bit14 14
#define R_SDRAM_CONFIG__bank_sel1__bit15 15
#define R_SDRAM_CONFIG__bank_sel1__bit16 16
#define R_SDRAM_CONFIG__bank_sel1__bit17 17
#define R_SDRAM_CONFIG__bank_sel1__bit18 18
#define R_SDRAM_CONFIG__bank_sel1__bit19 19
#define R_SDRAM_CONFIG__bank_sel1__bit20 20
#define R_SDRAM_CONFIG__bank_sel1__bit21 21
#define R_SDRAM_CONFIG__bank_sel1__bit22 22
#define R_SDRAM_CONFIG__bank_sel1__bit23 23
#define R_SDRAM_CONFIG__bank_sel1__bit24 24
#define R_SDRAM_CONFIG__bank_sel1__bit25 25
#define R_SDRAM_CONFIG__bank_sel1__bit26 26
#define R_SDRAM_CONFIG__bank_sel1__bit27 27
#define R_SDRAM_CONFIG__bank_sel1__bit28 28
#define R_SDRAM_CONFIG__bank_sel1__bit29 29
#define R_SDRAM_CONFIG__ca0__BITNR 5
#define R_SDRAM_CONFIG__ca0__WIDTH 3
#define R_SDRAM_CONFIG__bank_sel0__BITNR 0
#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5
#define R_SDRAM_CONFIG__bank_sel0__bit9 9
#define R_SDRAM_CONFIG__bank_sel0__bit10 10
#define R_SDRAM_CONFIG__bank_sel0__bit11 11
#define R_SDRAM_CONFIG__bank_sel0__bit12 12
#define R_SDRAM_CONFIG__bank_sel0__bit13 13
#define R_SDRAM_CONFIG__bank_sel0__bit14 14
#define R_SDRAM_CONFIG__bank_sel0__bit15 15
#define R_SDRAM_CONFIG__bank_sel0__bit16 16
#define R_SDRAM_CONFIG__bank_sel0__bit17 17
#define R_SDRAM_CONFIG__bank_sel0__bit18 18
#define R_SDRAM_CONFIG__bank_sel0__bit19 19
#define R_SDRAM_CONFIG__bank_sel0__bit20 20
#define R_SDRAM_CONFIG__bank_sel0__bit21 21
#define R_SDRAM_CONFIG__bank_sel0__bit22 22
#define R_SDRAM_CONFIG__bank_sel0__bit23 23
#define R_SDRAM_CONFIG__bank_sel0__bit24 24
#define R_SDRAM_CONFIG__bank_sel0__bit25 25
#define R_SDRAM_CONFIG__bank_sel0__bit26 26
#define R_SDRAM_CONFIG__bank_sel0__bit27 27
#define R_SDRAM_CONFIG__bank_sel0__bit28 28
#define R_SDRAM_CONFIG__bank_sel0__bit29 29

/*
!* External DMA registers
!*/

#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010)
#define R_EXT_DMA_0_CMD__cnt__BITNR 23
#define R_EXT_DMA_0_CMD__cnt__WIDTH 1
#define R_EXT_DMA_0_CMD__cnt__enable 1
#define R_EXT_DMA_0_CMD__cnt__disable 0
#define R_EXT_DMA_0_CMD__rqpol__BITNR 22
#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1
#define R_EXT_DMA_0_CMD__rqpol__ahigh 0
#define R_EXT_DMA_0_CMD__rqpol__alow 1
#define R_EXT_DMA_0_CMD__apol__BITNR 21
#define R_EXT_DMA_0_CMD__apol__WIDTH 1
#define R_EXT_DMA_0_CMD__apol__ahigh 0
#define R_EXT_DMA_0_CMD__apol__alow 1
#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1
#define R_EXT_DMA_0_CMD__rq_ack__burst 0
#define R_EXT_DMA_0_CMD__rq_ack__handsh 1
#define R_EXT_DMA_0_CMD__wid__BITNR 18
#define R_EXT_DMA_0_CMD__wid__WIDTH 2
#define R_EXT_DMA_0_CMD__wid__byte 0
#define R_EXT_DMA_0_CMD__wid__word 1
#define R_EXT_DMA_0_CMD__wid__dword 2
#define R_EXT_DMA_0_CMD__dir__BITNR 17
#define R_EXT_DMA_0_CMD__dir__WIDTH 1
#define R_EXT_DMA_0_CMD__dir__input 0
#define R_EXT_DMA_0_CMD__dir__output 1
#define R_EXT_DMA_0_CMD__run__BITNR 16
#define R_EXT_DMA_0_CMD__run__WIDTH 1
#define R_EXT_DMA_0_CMD__run__start 1
#define R_EXT_DMA_0_CMD__run__stop 0
#define R_EXT_DMA_0_CMD__trf_count__BITNR 0
#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16

#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010)
#define R_EXT_DMA_0_STAT__run__BITNR 16
#define R_EXT_DMA_0_STAT__run__WIDTH 1
#define R_EXT_DMA_0_STAT__run__start 1
#define R_EXT_DMA_0_STAT__run__stop 0
#define R_EXT_DMA_0_STAT__trf_count__BITNR 0
#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16

#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014)
#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28

#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018)
#define R_EXT_DMA_1_CMD__cnt__BITNR 23
#define R_EXT_DMA_1_CMD__cnt__WIDTH 1
#define R_EXT_DMA_1_CMD__cnt__enable 1
#define R_EXT_DMA_1_CMD__cnt__disable 0
#define R_EXT_DMA_1_CMD__rqpol__BITNR 22
#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1
#define R_EXT_DMA_1_CMD__rqpol__ahigh 0
#define R_EXT_DMA_1_CMD__rqpol__alow 1
#define R_EXT_DMA_1_CMD__apol__BITNR 21
#define R_EXT_DMA_1_CMD__apol__WIDTH 1
#define R_EXT_DMA_1_CMD__apol__ahigh 0
#define R_EXT_DMA_1_CMD__apol__alow 1
#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1
#define R_EXT_DMA_1_CMD__rq_ack__burst 0
#define R_EXT_DMA_1_CMD__rq_ack__handsh 1
#define R_EXT_DMA_1_CMD__wid__BITNR 18
#define R_EXT_DMA_1_CMD__wid__WIDTH 2
#define R_EXT_DMA_1_CMD__wid__byte 0
#define R_EXT_DMA_1_CMD__wid__word 1
#define R_EXT_DMA_1_CMD__wid__dword 2
#define R_EXT_DMA_1_CMD__dir__BITNR 17
#define R_EXT_DMA_1_CMD__dir__WIDTH 1
#define R_EXT_DMA_1_CMD__dir__input 0
#define R_EXT_DMA_1_CMD__dir__output 1
#define R_EXT_DMA_1_CMD__run__BITNR 16
#define R_EXT_DMA_1_CMD__run__WIDTH 1
#define R_EXT_DMA_1_CMD__run__start 1
#define R_EXT_DMA_1_CMD__run__stop 0
#define R_EXT_DMA_1_CMD__trf_count__BITNR 0
#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16

#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018)
#define R_EXT_DMA_1_STAT__run__BITNR 16
#define R_EXT_DMA_1_STAT__run__WIDTH 1
#define R_EXT_DMA_1_STAT__run__start 1
#define R_EXT_DMA_1_STAT__run__stop 0
#define R_EXT_DMA_1_STAT__trf_count__BITNR 0
#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16

#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c)
#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28

/*
!* Timer registers
!*/

#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020)
#define R_TIMER_CTRL__timerdiv1__BITNR 24
#define R_TIMER_CTRL__timerdiv1__WIDTH 8
#define R_TIMER_CTRL__timerdiv0__BITNR 16
#define R_TIMER_CTRL__timerdiv0__WIDTH 8
#define R_TIMER_CTRL__presc_timer1__BITNR 15
#define R_TIMER_CTRL__presc_timer1__WIDTH 1
#define R_TIMER_CTRL__presc_timer1__normal 0
#define R_TIMER_CTRL__presc_timer1__prescale 1
#define R_TIMER_CTRL__i1__BITNR 14
#define R_TIMER_CTRL__i1__WIDTH 1
#define R_TIMER_CTRL__i1__clr 1
#define R_TIMER_CTRL__i1__nop 0
#define R_TIMER_CTRL__tm1__BITNR 12
#define R_TIMER_CTRL__tm1__WIDTH 2
#define R_TIMER_CTRL__tm1__stop_ld 0
#define R_TIMER_CTRL__tm1__freeze 1
#define R_TIMER_CTRL__tm1__run 2
#define R_TIMER_CTRL__tm1__reserved 3
#define R_TIMER_CTRL__clksel1__BITNR 8
#define R_TIMER_CTRL__clksel1__WIDTH 4
#define R_TIMER_CTRL__clksel1__c300Hz 0
#define R_TIMER_CTRL__clksel1__c600Hz 1
#define R_TIMER_CTRL__clksel1__c1200Hz 2
#define R_TIMER_CTRL__clksel1__c2400Hz 3
#define R_TIMER_CTRL__clksel1__c4800Hz 4
#define R_TIMER_CTRL__clksel1__c9600Hz 5
#define R_TIMER_CTRL__clksel1__c19k2Hz 6
#define R_TIMER_CTRL__clksel1__c38k4Hz 7
#define R_TIMER_CTRL__clksel1__c57k6Hz 8
#define R_TIMER_CTRL__clksel1__c115k2Hz 9
#define R_TIMER_CTRL__clksel1__c230k4Hz 10
#define R_TIMER_CTRL__clksel1__c460k8Hz 11
#define R_TIMER_CTRL__clksel1__c921k6Hz 12
#define R_TIMER_CTRL__clksel1__c1843k2Hz 13
#define R_TIMER_CTRL__clksel1__c6250kHz 14
#define R_TIMER_CTRL__clksel1__cascade0 15
#define R_TIMER_CTRL__presc_ext__BITNR 7
#define R_TIMER_CTRL__presc_ext__WIDTH 1
#define R_TIMER_CTRL__presc_ext__prescale 0
#define R_TIMER_CTRL__presc_ext__external 1
#define R_TIMER_CTRL__i0__BITNR 6
#define R_TIMER_CTRL__i0__WIDTH 1
#define R_TIMER_CTRL__i0__clr 1
#define R_TIMER_CTRL__i0__nop 0
#define R_TIMER_CTRL__tm0__BITNR 4
#define R_TIMER_CTRL__tm0__WIDTH 2
#define R_TIMER_CTRL__tm0__stop_ld 0
#define R_TIMER_CTRL__tm0__freeze 1
#define R_TIMER_CTRL__tm0__run 2
#define R_TIMER_CTRL__tm0__reserved 3
#define R_TIMER_CTRL__clksel0__BITNR 0
#define R_TIMER_CTRL__clksel0__WIDTH 4
#define R_TIMER_CTRL__clksel0__c300Hz 0
#define R_TIMER_CTRL__clksel0__c600Hz 1
#define R_TIMER_CTRL__clksel0__c1200Hz 2
#define R_TIMER_CTRL__clksel0__c2400Hz 3
#define R_TIMER_CTRL__clksel0__c4800Hz 4
#define R_TIMER_CTRL__clksel0__c9600Hz 5
#define R_TIMER_CTRL__clksel0__c19k2Hz 6
#define R_TIMER_CTRL__clksel0__c38k4Hz 7
#define R_TIMER_CTRL__clksel0__c57k6Hz 8
#define R_TIMER_CTRL__clksel0__c115k2Hz 9
#define R_TIMER_CTRL__clksel0__c230k4Hz 10
#define R_TIMER_CTRL__clksel0__c460k8Hz 11
#define R_TIMER_CTRL__clksel0__c921k6Hz 12
#define R_TIMER_CTRL__clksel0__c1843k2Hz 13
#define R_TIMER_CTRL__clksel0__c6250kHz 14
#define R_TIMER_CTRL__clksel0__flexible 15

#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020)
#define R_TIMER_DATA__timer1__BITNR 24
#define R_TIMER_DATA__timer1__WIDTH 8
#define R_TIMER_DATA__timer0__BITNR 16
#define R_TIMER_DATA__timer0__WIDTH 8
#define R_TIMER_DATA__clkdiv_high__BITNR 8
#define R_TIMER_DATA__clkdiv_high__WIDTH 8
#define R_TIMER_DATA__clkdiv_low__BITNR 0
#define R_TIMER_DATA__clkdiv_low__WIDTH 8

#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022)
#define R_TIMER01_DATA__count__BITNR 0
#define R_TIMER01_DATA__count__WIDTH 16

#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022)
#define R_TIMER0_DATA__count__BITNR 0
#define R_TIMER0_DATA__count__WIDTH 8

#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023)
#define R_TIMER1_DATA__count__BITNR 0
#define R_TIMER1_DATA__count__WIDTH 8

#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024)
#define R_WATCHDOG__key__BITNR 1
#define R_WATCHDOG__key__WIDTH 3
#define R_WATCHDOG__enable__BITNR 0
#define R_WATCHDOG__enable__WIDTH 1
#define R_WATCHDOG__enable__stop 0
#define R_WATCHDOG__enable__start 1

#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0)
#define R_CLOCK_PRESCALE__ser_presc__BITNR 16
#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16
#define R_CLOCK_PRESCALE__tim_presc__BITNR 0
#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16

#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2)
#define R_SERIAL_PRESCALE__ser_presc__BITNR 0
#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16

#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0)
#define R_TIMER_PRESCALE__tim_presc__BITNR 0
#define R_TIMER_PRESCALE__tim_presc__WIDTH 16

#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0)
#define R_PRESCALE_STATUS__ser_status__BITNR 16
#define R_PRESCALE_STATUS__ser_status__WIDTH 16
#define R_PRESCALE_STATUS__tim_status__BITNR 0
#define R_PRESCALE_STATUS__tim_status__WIDTH 16

#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2)
#define R_SER_PRESC_STATUS__ser_status__BITNR 0
#define R_SER_PRESC_STATUS__ser_status__WIDTH 16

#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0)
#define R_TIM_PRESC_STATUS__tim_status__BITNR 0
#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16

#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4)
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0
#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0
#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1
#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3
#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0
#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1
#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2
#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3
#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4
#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5
#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6
#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7
#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1
#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0
#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1
#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4
#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10

/*
!* Shared RAM interface registers
!*/

#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040)
#define R_SHARED_RAM_CONFIG__width__BITNR 3
#define R_SHARED_RAM_CONFIG__width__WIDTH 1
#define R_SHARED_RAM_CONFIG__width__byte 0
#define R_SHARED_RAM_CONFIG__width__word 1
#define R_SHARED_RAM_CONFIG__enable__BITNR 2
#define R_SHARED_RAM_CONFIG__enable__WIDTH 1
#define R_SHARED_RAM_CONFIG__enable__yes 1